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WIP DNM esp32: add flash cache support #8783
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WIP DNM esp32: add flash cache support #8783
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Codecov Report
@@ Coverage Diff @@
## master #8783 +/- ##
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- Coverage 52.83% 52.41% -0.43%
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Files 310 198 -112
Lines 45311 24912 -20399
Branches 10468 5185 -5283
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- Hits 23942 13058 -10884
+ Misses 16584 9754 -6830
+ Partials 4785 2100 -2685
Continue to review full report at Codecov.
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Add flash cache support for esp32. Signed-off-by: Gautier Seidel <[email protected]>
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Nice catch on the pinmux code!
I think it's fine if we have two linker scripts, at least short term. Long term, it should be better to only support building with flash cache enabled; otherwise, it's kind of hard to utilize the full potential of this SoC.
Patch LGTM, but I have a few questions.
arch/xtensa/soc/esp32/linker.ld
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*(.literal.*_int_handler .text.*_int_handler) | ||
*(.literal.*_irq_spurious .text.*_irq_spurious) | ||
*(.literal.*i2c_esp32_isr .text.*i2c_esp32_isr) |
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Might be a better idea to mark ISRs in ESP32 drivers with an __attribute__(__section__("IRAM"))
or something of the sort; otherwise, for each driver for this platform, we'll need to add a line here. It would be great if we had a libdrivers.a
to make this even easier.
Also, I'm curious here: say that someone writes an application using the GPIO ports, and they register a callback. Those are executed in interrupt context. If they end up calling a function that happens to not be in the flash cache, what is going to happen?
arch/xtensa/soc/esp32/linker.ld
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@@ -202,12 +209,23 @@ SECTIONS | |||
*(.dynamic) | |||
*(.gnu.version_d) | |||
. = ALIGN(4); /* this table MUST be 4-byte aligned */ | |||
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__devconfig_start = .; |
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These are very much Zephyr-specific; don't we have linker macros for this sort of thing?
arch/xtensa/soc/esp32/linker.ld
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iram0_2_seg(RX): org = 0x400D0018, len = 0x330000 | ||
dram0_0_seg(RW): org = 0x3FFB0000, len = 0x50000 | ||
iram0_2_seg(RX): org = 0x400D0018, len = 0x330000-18 | ||
dram0_0_seg(RW): org = 0x3FFB0000, len = 0x2c200 |
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Might be a good idea to explain what's the meaning for -18
and why the dram0_0_seg
went from 0x50000
bytes to 0x2c200
. I can imagine there are reasons, but linker scripts are tricky and it's best to be as clear as possible with these values.
drivers/pinmux/pinmux_esp32.c
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pinmux_set(NULL, pin, 0); | ||
/* pin 6 to 11 are configured for SPI by the second stage bootloader. | ||
* We should not change them, otherwise we can't access the flash | ||
* anymore. */ |
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If the point here is to disallow software from ever touching those pins through this driver, you probably want to put that rule into pinmux_set(), no?
Honestly, I'm not sure I see much value to this initialization loop anyway. If we have code enabled that cares about particular pin state, it will set it in its own initialization. If not, it's probably better to rely on whatever the bootloader set for us. Forcing "function zero" to be the default for everyone always is just going to cause collisions like this. Maybe just remove the loop?
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I updated the comment. The idea is to keep the ability to reconfigure these pins during run-time.
Added in board Kconfig for esp32 Signed-off-by: Gautier Seidel <[email protected]>
esp32 pinmux driver doesn't re-initialize the SPI pins if flash cache is used. Signed-off-by: Gautier Seidel <[email protected]>
Now two linker scripts are available: one with flash cache suport, one without. Signed-off-by: Gautier Seidel <[email protected]>
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@GautierAtWork This PR seems to have been getting stale for very long. |
Needs option
CONFIG_BOOTLOADER_ESP_IDF
Closes #3722
todo:
#ifdef
around changes inpinmux_esp32.c
@lpereira: an option like
CONFIG_ESP32_FLASH_CACHE
will be introduced. Two linker scripts will exist then: one with data cache, one without data cache. Will it be ok for you?