boards: ruiside: art-pi2: add minimum support #88185
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dts/bindings/vendor-prefixes.txt
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| @@ -578,6 +578,7 @@ ronbo Ronbo Electronics | |||
| ronoth Ronoth | |||
| roofull Shenzhen Roofull Technology Co, Ltd | |||
| roseapplepi RoseapplePi.org | |||
| rt-thread RT-Thread | |||
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I recommend using the foundation's name, if available.
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It's a company, Shanghai Ruiside Electronic Technology Co., Ltd. https://www.rt-thread.org/about.html
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Weirdly, there is another entity Real-Thread Information Technology Limited mentioned here https://www.rt-thread.org/account/user/terms.html
and here https://www.rt-thread.io/account/user/policy.html
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I think Shanghai Ruiside Electronic Technology Co., Ltd. is the correct company name. RT-Thread is a trademark owned by this company, as states in this official article (in Chinese). Also in China, this company is the official distributor and manufacturer of RT-Thread boards, including the ART-Pi2.
boards/rt-thread/art_pi2/board.yml
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| board: | |||
| name: art_pi2 | |||
| full_name: RT-Thread ART-Pi2 | |||
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| full_name: RT-Thread ART-Pi2 | |
| full_name: ART-Pi2 |
What's more, I cannot find any reference to this board online -- is this really how the board is named or is this a "rev. 2" of the ART-Pi?
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I prefer taking this as separate board named "ART-Pi2", distinct from ART-Pi with different mcu and other features.
Documentation can be found here: sdk-bsp-stm32h7r-realthread-artpi2
Schematics are available here: schematics
For clarity:
- ART-Pi2:
- New board featuring STM32H7R7 (this PR)
- Just released in February, 2025, so there is not much reference online
- Will be available on AliExpress and Mouser soon
- ART-Pi:
- Different board featuring STM32H750, released in 2020
- Available on AliExpress and Mouser
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Great, thanks for clarifying!
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Why is this vendor using the name RT-Thread, which is a well-known open-source RTOS? https://en.m.wikipedia.org/wiki/RT-Thread
Is this coming from the same company?
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Yes, this board comes from the same company that created RT-Thread RTOS. These development boards (ART-Pi and ART-Pi2) are officially designed and produced by the RT-Thread team to showcase their RTOS capabilities and provide reference hardware for developers. While the board's original SDK is based on RT-Thread RTOS, I'm working on porting it to Zephyr to provide users with an alternative RTOS option. |
| :goals: debug | ||
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| .. _ART-Pi2 website: | ||
| https://github.com/RT-Thread-Studio/sdk-bsp-stm32h7r-realthread-artpi2 |
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Should we be referencing repos dedicated to other RTOSs in Zephyr?
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Why not?
@kartben just wondering if it's really necessary, that's all.
| https://www.st.com/resource/en/reference_manual/rm0477-stm32h7rx7sx-armbased-32bit-mcus-stmicroelectronics.pdf | ||
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| .. _ART-Pi2 board documents: | ||
| https://github.com/RT-Thread-Studio/sdk-bsp-stm32h7r-realthread-artpi2/tree/master/documents |
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Most of the info found here is specific to RT-Thread RTOS (plus not in English). Info that is relevant to Zephyr should be added in the board's doc directly & this reference should be removed.
| https://github.com/RT-Thread-Studio/sdk-bsp-stm32h7r-realthread-artpi2/tree/master/documents | ||
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| .. _OpenOCD installing Debug Version: | ||
| https://github.com/zephyrproject-rtos/openocd |
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not used, to be removed.
| https://github.com/zephyrproject-rtos/openocd | ||
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| .. _OpenOCD installing with ST-LINK V3 support: | ||
| https://mbd.kleier.net/integrating-st-link-v3.html |
| https://mbd.kleier.net/integrating-st-link-v3.html | ||
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| .. _STM32CubeIDE: | ||
| https://www.st.com/en/development-tools/stm32cubeide.html |
| Debugging | ||
| ========= | ||
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| You can debug an application in the usual way. Here is an example for the |
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with OpenOCD? if yes, is it the one included with Zephyr SDK on Linux?
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actually debuging and flashing don't work with the OpenOCD included with Zephyr SDK on Linux, removed it, thank you
| The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, | ||
| so its :ref:`installation <stm32cubeprog-flash-host-tools>` is required. | ||
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| Alternatively, pyocd or openocd can also be used to flash the board using |
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dts/bindings/vendor-prefixes.txt
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| @@ -578,6 +578,7 @@ ronbo Ronbo Electronics | |||
| ronoth Ronoth | |||
| roofull Shenzhen Roofull Technology Co, Ltd | |||
| roseapplepi RoseapplePi.org | |||
| rt-thread Shanghai Ruiside Electronic Technology Co., Ltd. | |||
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rt-thread -> ruiside, the same for board folder name.
boards/rt-thread/art_pi2/art_pi2.dts
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| #include <zephyr/dt-bindings/input/input-event-codes.h> | ||
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| / { | ||
| model = "RT-Thread ART-Pi2 board"; |
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| model = "RT-Thread ART-Pi2 board"; | |
| model = "Ruiside Electronic ART-Pi2 board"; |
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boards/ruiside/art_pi2/art_pi2.dts
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| / { | ||
| model = "Ruiside Electronic ART-Pi2 board"; | ||
| compatible = "Ruiside,art-pi2"; |
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| compatible = "Ruiside,art-pi2"; | |
| compatible = "ruiside,art-pi2"; |
boards/ruiside/art_pi2/art_pi2.yaml
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| - watchdog | ||
| - adc | ||
| - entropy | ||
| vendor: Ruiside |
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| vendor: Ruiside | |
| vendor: ruiside |
| # Enable HW stack protection | ||
| CONFIG_HW_STACK_PROTECTION=y | ||
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| # enable uart driver |
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Use proper capitalization of nouns in code comments (e.g. UART and not uart, CMake and not cmake).
And use capitals for first letter of comments
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About:
The commit you're pointing at is merged in hal_stm32 already. Can you clarify the expectation here ? |
It seems like this commit anly add |
boards/ruiside/art_pi2/doc/index.rst
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| - Core: ARM |reg| 32-bit Cortex |reg| -M7 CPU with TrustZone |reg| and FPU. | ||
| - Performance benchmark: | ||
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| - 1284 DMPIS/MHz (Dhrystone 2.1) | ||
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| - Security | ||
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| - Arm |reg| TrustZone |reg| with ARMv8-M mainline security extension | ||
| - Up to 8 configurable SAU regions | ||
| - TrustZone |reg| aware and securable peripherals | ||
| - Flexible lifecycle scheme with secure debug authentication | ||
| - Preconfigured immutable root of trust (ST-iROT) | ||
| - SFI (secure firmware installation) | ||
| - Secure data storage with hardware unique key (HUK) | ||
| - Secure firmware upgrade support with TF-M | ||
| - 2x AES coprocessors including one with DPA resistance | ||
| - Public key accelerator, DPA resistant | ||
| - On-the-fly decryption of Octo-SPI external memories | ||
| - HASH hardware accelerator | ||
| - True random number generator, NIST SP800-90B compliant | ||
| - 96-bit unique ID | ||
| - Active tampers | ||
| - True Random Number Generator (RNG) NIST SP800-90B compliant | ||
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| - Clock management: | ||
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| - 24 MHz crystal oscillator (HSE) | ||
| - 32768 Hz crystal oscillator for RTC (LSE) | ||
| - Internal 64 MHz (HSI) trimmable by software | ||
| - Internal low-power 32 kHz RC (LSI)( |plusminus| 5%) | ||
| - Internal 4 MHz oscillator (CSI), trimmable by software | ||
| - Internal 48 MHz (HSI48) with recovery system | ||
| - 3 PLLs for system clock, USB, audio, ADC | ||
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| - Power management | ||
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| - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry | ||
| - Embedded SMPS step-down converter | ||
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| - RTC with HW calendar, alarms and calibration | ||
| - Up to 152 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V | ||
| - Up to 16 timers and 2 watchdogs | ||
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| - 16x 16-bit | ||
| - 4x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input | ||
| - 5x 16-bit low-power 16-bit timers (available in Stop mode) | ||
| - 2x watchdogs | ||
| - 1x SysTick timer | ||
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| - Memories | ||
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| - Up to 64KB Flash, 2 banks read-while-write | ||
| - 1 Kbyte OTP (one-time programmable) | ||
| - 640 KB of SRAM including 64 KB with hardware parity check and 320 Kbytes with flexible ECC | ||
| - 4 Kbytes of backup SRAM available in the lowest power modes | ||
| - Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories | ||
| - 2x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats | ||
| - 1x HEXASPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats | ||
| - 2x SD/SDIO/MMC interfaces | ||
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| - Rich analog peripherals (independent supply) | ||
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| - 2x 12-bit ADC with up to 5 MSPS in 12-bit | ||
| - 1x Digital temperature sensor | ||
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| - 35x communication interfaces | ||
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| - 1x USB Type-C / USB power-delivery controller | ||
| - 1x USB OTG full-speed with PHY | ||
| - 1x USB OTG high-speed with PHY | ||
| - 3x I2C FM+ interfaces (SMBus/PMBus) | ||
| - 1x I3C interface | ||
| - 7x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control) | ||
| - 2x LP UART | ||
| - 6x SPIs including 3 muxed with full-duplex I2S | ||
| - 2x SAI | ||
| - 2x FDCAN | ||
| - 2x SD/SDIO/MMC interface | ||
| - 2x 16 channel DMA controllers | ||
| - 1x 8- to 16- bit camera interface | ||
| - 1x HDMI-CEC | ||
| - 1x Ethernel MAC interface with DMA controller | ||
| - 1x 16-bit parallel slave synchronous-interface | ||
| - 1x SPDIF-IN interface | ||
| - 1x MDIO slave interface | ||
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| - CORDIC for trigonometric functions acceleration | ||
| - FMAC (filter mathematical accelerator) | ||
| - CRC calculation unit | ||
| - Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| | ||
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This is taking 2 pages on the documentation page, I would just remove it. People should click on "More information..." links if they need more info, and doc page shouldn't be unnecessarily cluttered by these.
| - Core: ARM |reg| 32-bit Cortex |reg| -M7 CPU with TrustZone |reg| and FPU. | |
| - Performance benchmark: | |
| - 1284 DMPIS/MHz (Dhrystone 2.1) | |
| - Security | |
| - Arm |reg| TrustZone |reg| with ARMv8-M mainline security extension | |
| - Up to 8 configurable SAU regions | |
| - TrustZone |reg| aware and securable peripherals | |
| - Flexible lifecycle scheme with secure debug authentication | |
| - Preconfigured immutable root of trust (ST-iROT) | |
| - SFI (secure firmware installation) | |
| - Secure data storage with hardware unique key (HUK) | |
| - Secure firmware upgrade support with TF-M | |
| - 2x AES coprocessors including one with DPA resistance | |
| - Public key accelerator, DPA resistant | |
| - On-the-fly decryption of Octo-SPI external memories | |
| - HASH hardware accelerator | |
| - True random number generator, NIST SP800-90B compliant | |
| - 96-bit unique ID | |
| - Active tampers | |
| - True Random Number Generator (RNG) NIST SP800-90B compliant | |
| - Clock management: | |
| - 24 MHz crystal oscillator (HSE) | |
| - 32768 Hz crystal oscillator for RTC (LSE) | |
| - Internal 64 MHz (HSI) trimmable by software | |
| - Internal low-power 32 kHz RC (LSI)( |plusminus| 5%) | |
| - Internal 4 MHz oscillator (CSI), trimmable by software | |
| - Internal 48 MHz (HSI48) with recovery system | |
| - 3 PLLs for system clock, USB, audio, ADC | |
| - Power management | |
| - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry | |
| - Embedded SMPS step-down converter | |
| - RTC with HW calendar, alarms and calibration | |
| - Up to 152 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V | |
| - Up to 16 timers and 2 watchdogs | |
| - 16x 16-bit | |
| - 4x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input | |
| - 5x 16-bit low-power 16-bit timers (available in Stop mode) | |
| - 2x watchdogs | |
| - 1x SysTick timer | |
| - Memories | |
| - Up to 64KB Flash, 2 banks read-while-write | |
| - 1 Kbyte OTP (one-time programmable) | |
| - 640 KB of SRAM including 64 KB with hardware parity check and 320 Kbytes with flexible ECC | |
| - 4 Kbytes of backup SRAM available in the lowest power modes | |
| - Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories | |
| - 2x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats | |
| - 1x HEXASPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats | |
| - 2x SD/SDIO/MMC interfaces | |
| - Rich analog peripherals (independent supply) | |
| - 2x 12-bit ADC with up to 5 MSPS in 12-bit | |
| - 1x Digital temperature sensor | |
| - 35x communication interfaces | |
| - 1x USB Type-C / USB power-delivery controller | |
| - 1x USB OTG full-speed with PHY | |
| - 1x USB OTG high-speed with PHY | |
| - 3x I2C FM+ interfaces (SMBus/PMBus) | |
| - 1x I3C interface | |
| - 7x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control) | |
| - 2x LP UART | |
| - 6x SPIs including 3 muxed with full-duplex I2S | |
| - 2x SAI | |
| - 2x FDCAN | |
| - 2x SD/SDIO/MMC interface | |
| - 2x 16 channel DMA controllers | |
| - 1x 8- to 16- bit camera interface | |
| - 1x HDMI-CEC | |
| - 1x Ethernel MAC interface with DMA controller | |
| - 1x 16-bit parallel slave synchronous-interface | |
| - 1x SPDIF-IN interface | |
| - 1x MDIO slave interface | |
| - CORDIC for trigonometric functions acceleration | |
| - FMAC (filter mathematical accelerator) | |
| - CRC calculation unit | |
| - Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| |
| :maybe-skip-config: | ||
| :goals: debug | ||
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| .. _ART-Pi2 website: |
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| .. _ART-Pi2 website: | |
| References | |
| ********** | |
| .. target-notes:: | |
| .. _ART-Pi2 website: |
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rebased to main to address dependency issue, dear reviewers please revisits. |
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For future note: to get reviewers to know they need to check things, in the top right under reviewers, click the refresh button next to the names, have done it for you |
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- introduced a new vendor ruiside, updated `dts/bindings/vendor-prefixes.txt` - add art-pi2 board basic support Signed-off-by: Shan Pen <[email protected]>
Changes proposed:
dts/bindings/vendor-prefixes.txtwith rt-threat prefixSTM32H7R7L8HxHmicrocontrollerPOWER_SUPPLY_DIRECT_SMPSoperation modeTesting:
Hello World Sample Output
# Required HAL Changes:- Need to addSMPSdefine in hal_stm32 to enable POWER_SUPPLY_DIRECT_SMPS, otherwise this won't buildwith flollowing error
Questions for Maintainers: