drivers: serial: ns16550: Fix FIFO detection on Xilinx 16550 #88468
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The Xilinx AXI UART16550 FPGA IP core seems to have a quirk where the first read of the combined FCR/IIR register, after FCR is written when configuring the port, just reads back FCR (which is only supposed to happen when the DLAB bit in LCR is set) rather than reading the IIR register. This causes the code using the IIR register for detecting FIFO support to misbehave and not detect that a FIFO is present. Add a dummy read of the IIR register before the real one to avoid this problem. This is expected to be harmless on other implementations. Signed-off-by: Robert Hancock <[email protected]>
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Shouldn't this be fixed in the IP since it's soft IP on FPGA? |
Ideally, but this IP is probably burned into a lot of logic builds by now, and Xilinx seems reluctant to make changes to some of these long-standing IP cores, (presumably) especially when it can be worked around in software. I'm not 100% sure why Linux (for example) doesn't hit this, but presumably the initialization sequence is slightly different such that it doesn't run into this problem. |
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Ping.. any feedback? |
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Might be a good idea to wrap it with a kconfig. Or even better with devicetree where, if any UART instance is from Xilinx, do the extra read. For non-Xilinx UART, this is an unnecessary read so it is better to limit it to where it is actually needed. |
The Xilinx AXI UART16550 FPGA IP core seems to have a quirk where the first read of the combined FCR/IIR register, after FCR is written when configuring the port, just reads back FCR (which is only supposed to happen when the DLAB bit in LCR is set) rather than reading the IIR register. This causes the code using the IIR register for detecting FIFO support to misbehave and not detect that a FIFO is present.
Add a dummy read of the IIR register before the real one to avoid this problem. This is expected to be harmless on other implementations.