Add minimal support for Renesas RZ/A2M EVK

boards/renesas/rza2m_evk/Kconfig.rza2m_evk

@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RZA2M_EVK
+	select SOC_R7S921053VCBG

boards/renesas/rza2m_evk/board.cmake

@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R7S921053VCBG")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/renesas/rza2m_evk/board.yml

@@ -0,0 +1,6 @@
+board:
+  name: rza2m_evk
+  full_name: RZ/A2M Evaluation Kit
+  vendor: renesas
+  socs:
+  - name: r7s921053vcbg

boards/renesas/rza2m_evk/doc/index.rst

@@ -0,0 +1,73 @@
+.. zephyr:board:: rza2m_evk
+
+Overview
+********
+
+The RZ/A2M Evaluation Board Kit is a best evaluation board kit to evaluate RZ/A2M.
+
+* On-board device: RZ/A2M (R7S921053VCBG: with DRP function, without encryption function, internal
+  RAM 4MB) Evaluation of DRP (Dynamically Reconfigurable Processor) is possible.
+* MIPI Camera Module (MIPI CSI) is bundled and image recognition processing etc. can be used with
+  images input with MIPI camera.
+* HyperMCP (Multi-chip package), in which HyperFlash and HyperRAM are installed in one package,
+  is mounted. HyperFlash and HyperRAM can be evaluated.
+* A Display Output Board is included and the graphic output is possible by connecting it to the
+  external display.
+* It is possible to evaluate 2ch Ethernet communication.
+* Other peripheral functions such as SDHI and USB can also be evaluated.
+* Allows for safe and secure connection to the AWS cloud.
+  HyperFlash and HyperRAM are trademarks of Cypress Semiconductor Corporation of the U.S.
+
+Hardware
+********
+
+The Renesas RZ/A2M MPU documentation can be found at `RZ/A2M Group Website`_
+
+.. figure:: rza2m_block_diagram.webp
+	:width: 600px
+	:align: center
+	:alt: RZ/A2M group feature
+
+	RZ/A2M block diagram (Credit: Renesas Electronics Corporation)
+
+Detailed hardware features for the board can be found at `RZ/A2M-EVK Website`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``rza2m_evk`` board configuration can be
+built and flashed in the usual way (see :ref:`build_an_application`
+and :ref:`application_run` for more details).
+
+Console
+=======
+
+The UART port is accessed by USB-Serial port (CN5).
+
+Building & Flashing
+===================
+
+Here is an example for building and flashing the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: rza2m_evk
+   :goals: build flash
+
+References
+**********
+
+.. target-notes::
+
+.. _RZ/A2M Group Website:
+   https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rza2m-image-processing-rtos-mpu-drp-and-4mb-chip-ram
+
+.. _RZ/A2M-EVK Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rza2m-evkit-rza2m-evaluation-kit

boards/renesas/rza2m_evk/rza2m_evk-pinctrl.dtsi

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza2m.h>
+
+&pinctrl {
+	/omit-if-no-ref/ scif4_default: scif4_default {
+		scif4-pinmux {
+			pinmux = <RZA2M_PINMUX(PORT_09, 0, 4)>, /* TXD */
+				 <RZA2M_PINMUX(PORT_09, 1, 4)>; /* RXD */
+		};
+	};
+};

boards/renesas/rza2m_evk/rza2m_evk.dts

@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <arm/renesas/rz/rza/r7s9210.dtsi>
+#include <freq.h>
+#include "rza2m_evk-pinctrl.dtsi"
+
+/ {
+	model = "Renesas RZA2M EVK";
+	compatible = "renesas,rza2m_evk";
+
+	chosen {
+		zephyr,sram = &ram;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,console = &scif4;
+		zephyr,shell-uart = &scif4;
+	};
+
+	aliases {
+		led0 = &led1_green;
+		led1 = &led1_red;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1_red: led1_red {
+			gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
+		};
+
+		led1_green: led1_green {
+			gpios = <&gpioc 1 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	flash0: flash@20000000 {
+		compatible = "mmio-sram";
+		reg = <0x20000000 DT_SIZE_M(64)>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			loader_program: partition@0 {
+				label = "loader-program";
+				reg = <0x00000000 DT_SIZE_K(56)>;
+				read-only;
+			};
+
+			slot0_partition: partition@E000  {
+				label = "image-0";
+				reg = <0x0000E000 (DT_SIZE_M(64) - DT_SIZE_K(56))>;
+				read-only;
+			};
+		};
+	};
+};
+
+&osc {
+	clock-frequency = <DT_FREQ_M(24)>;
+};
+
+&iclk {
+	clock-frequency = <DT_FREQ_M(528)>;
+};
+
+&bclk {
+	clock-frequency = <DT_FREQ_M(132)>;
+};
+
+&p1clk {
+	clock-frequency = <DT_FREQ_M(66)>;
+};
+
+&ostm0 {
+	status = "okay";
+};
+
+/* Currently, the maximum supported baud rate on the USB Micro port (CN5) is 115200 */
+&scif4 {
+	pinctrl-0 = <&scif4_default>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};

boards/renesas/rza2m_evk/rza2m_evk.yaml

@@ -0,0 +1,11 @@
+identifier: rza2m_evk
+name: RZ/A2M Evaluation Kit
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - uart
+  - gpio
+vendor: renesas

boards/renesas/rza2m_evk/rza2m_evk_defconfig

@@ -0,0 +1,15 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_XIP=n
+
+# Enable clock control
+CONFIG_CLOCK_CONTROL=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y

drivers/clock_control/CMakeLists.txt

@@ -52,6 +52,11 @@ if(CONFIG_CLOCK_CONTROL_NRF2)
   zephyr_library_sources(clock_control_nrf2_lfclk.c)
 endif()
 
+if(CONFIG_CLOCK_CONTROL_RENESAS_RZA2M_CPG)
+  zephyr_library_sources(clock_control_renesas_rza2m_cpg.c)
+  zephyr_library_sources(clock_control_renesas_rza2m_cpg_lld.c)
+endif()
+
 if(CONFIG_CLOCK_CONTROL_STM32_CUBE)
   zephyr_library_sources_ifdef(CONFIG_CLOCK_STM32_MUX clock_stm32_mux.c)
   zephyr_library_sources_ifdef(CONFIG_CLOCK_STM32_MCO clock_stm32_mco.c)

drivers/clock_control/Kconfig.renesas_rz_cpg

@@ -1,4 +1,4 @@
-# Copyright (c) 2024 Renesas Electronics Corporation
+# Copyright (c) 2024-2025 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 config CLOCK_CONTROL_RENESAS_RZ_CPG
@@ -10,3 +10,10 @@ config CLOCK_CONTROL_RENESAS_RZ_CPG
 	  Enable support for Renesas RZ CPG Clock Pulse Generator (CPG) driver.
 	  The CPG driver supports only module's clocks.
 	  The PLLs and core clocks are not configured by the CPG driver.
+
+config CLOCK_CONTROL_RENESAS_RZA2M_CPG
+	bool "Renesas RZ/A2M Clock Control Driver"
+	default y
+	depends on DT_HAS_RENESAS_RZA2M_CPG_ENABLED
+	help
+	  Enable support for Renesas RZ/A2M CPG Clock Pulse Generator (CPG) driver.

drivers/clock_control/clock_control_renesas_rza2m_cpg.c

@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_rza2m_cpg
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/clock_control.h>
+#include "clock_control_renesas_rza2m_cpg_lld.h"
+
+static int clock_control_renesas_rza2m_on_off(const struct device *dev, clock_control_subsys_t sys,
+					      bool enable)
+{
+	if (!dev || !sys) {
+		return -EINVAL;
+	}
+
+	int ret = -EINVAL;
+	uint32_t *clock_id = (uint32_t *)sys;
+	uint32_t clk_module = RZA2M_GET_MODULE(*clock_id);
+
+	ret = rza2m_cpg_mstp_clock_endisable(dev, clk_module, enable);
+
+	return ret;
+}
+
+static int clock_control_renesas_rza2m_on(const struct device *dev, clock_control_subsys_t sys)
+{
+	/* Enable the specified clock */
+	return clock_control_renesas_rza2m_on_off(dev, sys, true);
+}
+
+static int clock_control_renesas_rza2m_off(const struct device *dev, clock_control_subsys_t sys)
+{
+	/* Disable the specified clock */
+	return clock_control_renesas_rza2m_on_off(dev, sys, false);
+}
+
+static int clock_control_renesas_rza2m_get_rate(const struct device *dev,
+						clock_control_subsys_t sys, uint32_t *rate)
+{
+	if (!dev || !sys || !rate) {
+		return -EINVAL;
+	}
+
+	int ret = -EINVAL;
+	uint32_t *clock_id = (uint32_t *)sys;
+	enum rza2m_cpg_get_freq_src clk_src = RZA2M_GET_CLOCK_SRC(*clock_id);
+
+	ret = rza2m_cpg_get_clock(dev, clk_src, rate);
+
+	return ret;
+}
+
+static int clock_control_renesas_rza2m_set_rate(const struct device *dev,
+						clock_control_subsys_t sys,
+						clock_control_subsys_rate_t rate)
+{
+	int ret;
+	enum rza2m_cp_sub_clock clock_name = (enum rza2m_cp_sub_clock)sys;
+	uint32_t clock_rate = (uint32_t)rate;
+
+	ret = rza2m_cpg_set_sub_clock_divider(dev, clock_name, clock_rate);
+
+	return ret;
+}
+
+static int clock_control_renesas_rza2m_init(const struct device *dev)
+{
+	const struct rza2m_cpg_clock_config *config = dev->config;
+	uint16_t reg_val;
+
+	DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
+	rza2m_cpg_calculate_pll_frequency(dev);
+	/* Select Bφ Clock output for CLKIO */
+	sys_write16(0, CPG_REG_ADDR(CPG_CKIOSEL_OFFSET));
+
+	/* Enable CLKIO as Low-level output */
+	reg_val = sys_read16(CPG_REG_ADDR(CPG_FRQCR_OFFSET));
+	reg_val &= ~(CPG_FRQCR_CKOEN | CPG_FRQCR_CKOEN2);
+	reg_val |= (1U << CPG_FRQCR_CKOEN_SHIFT) | (1U << CPG_FRQCR_CKOEN2_SHIFT);
+	sys_write16(reg_val, CPG_REG_ADDR(CPG_FRQCR_OFFSET));
+
+	rza2m_cpg_set_sub_clock_divider(dev, CPG_SUB_CLOCK_ICLK, config->cpg_iclk_freq_hz_cfg);
+	rza2m_cpg_set_sub_clock_divider(dev, CPG_SUB_CLOCK_BCLK, config->cpg_bclk_freq_hz_cfg);
+	rza2m_cpg_set_sub_clock_divider(dev, CPG_SUB_CLOCK_P1CLK, config->cpg_p1clk_freq_hz_cfg);
+
+	return 0;
+}
+static DEVICE_API(clock_control, rza2m_clock_control_driver_api) = {
+	.on = clock_control_renesas_rza2m_on,
+	.off = clock_control_renesas_rza2m_off,
+	.get_rate = clock_control_renesas_rza2m_get_rate,
+	.set_rate = clock_control_renesas_rza2m_set_rate,
+};
+
+static const struct rza2m_cpg_clock_config g_rza2m_cpg_clock_config = {
+	DEVICE_MMIO_ROM_INIT(DT_DRV_INST(0)),
+	.cpg_extal_freq_hz_cfg = DT_INST_PROP_BY_PHANDLE(0, clocks, clock_frequency),
+	.cpg_iclk_freq_hz_cfg = DT_PROP(DT_NODELABEL(iclk), clock_frequency),
+	.cpg_bclk_freq_hz_cfg = DT_PROP(DT_NODELABEL(bclk), clock_frequency),
+	.cpg_p1clk_freq_hz_cfg = DT_PROP(DT_NODELABEL(p1clk), clock_frequency),
+};
+
+static struct rza2m_cpg_clock_data g_rza2m_cpg_clock_data;
+
+DEVICE_DT_INST_DEFINE(0, clock_control_renesas_rza2m_init, NULL, &g_rza2m_cpg_clock_data,
+		      &g_rza2m_cpg_clock_config, PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
+		      &rza2m_clock_control_driver_api);