soc: nxp: mcxn: configure CPU1 TrustZone access level

[DerekSnell]

Configures AHBSC MASTER_SEC_LEVEL register for the cpu1 before cpu1 is enabled. By default, this gives CPU1 secure and privileged access to the rest of the SOC, same as CPU0.

This also reverts feb966d. Configuring the GPIO access permissions is no longer required for CPU1 to access the GPIO.

Resolves #88965 .

Tested using the blinky sample running on CPU1 using the following commands:

west build -b frdm_mcxn947//cpu1 samples/basic/blinky -d blinky_cpu1 -p -- -DCONFIG_SECOND_CORE_MCUX=y
west flash -d blinky_cpu1
west build -b frdm_mcxn947//cpu0 samples/hello_world/  -d hello_cpu0_loader -p -- -DCONFIG_SECOND_CORE_MCUX=y
west flash -d hello_cpu0_loader

GPIO also accessible from CPU0, tested with sample blinky and button.

[DerekSnell]

@alxrey and @ubieda , FYI

[ubieda]

I just tested and confirmed it fixes the regression. Thanks!

[alxrey]

Bits 3-2 (CPU1 field) are cleared by the mask & 0x3FFFFFF3U, which doesn't seem to be the intended behavior.

If COP1 in MASTER_SEC_LEVEL is set to 1 or 2 (Non-secure and privileged Master, respectively Secure and non-privileged Master), MASTER_SEC_ANTI_POL_REG will not have the inverse polarity of MASTER_SEC_LEVEL as specified.

IMHO, the mask should be set to 0x3FFFFFFFU.

[alxrey]

Shouldn't macros be used instead of hard-coded values?

Concretely:

AHBSC->MASTER_SEC_ANTI_POL_REG = (~AHBSC->MASTER_SEC_LEVEL & ~AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) | AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(2);