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Merged
merged 1 commit into from
Apr 11, 2021
Merged

Rename various SIMD load instructions #3795

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12 changes: 6 additions & 6 deletions scripts/gen-s-parser.py
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Expand Up @@ -475,18 +475,18 @@
("i32x4.trunc_sat_f32x4_u", "makeUnary(s, UnaryOp::TruncSatUVecF32x4ToVecI32x4)"),
("f32x4.convert_i32x4_s", "makeUnary(s, UnaryOp::ConvertSVecI32x4ToVecF32x4)"),
("f32x4.convert_i32x4_u", "makeUnary(s, UnaryOp::ConvertUVecI32x4ToVecF32x4)"),
("v128.load8_splat", "makeSIMDLoad(s, SIMDLoadOp::LoadSplatVec8x16)"),
("v128.load16_splat", "makeSIMDLoad(s, SIMDLoadOp::LoadSplatVec16x8)"),
("v128.load32_splat", "makeSIMDLoad(s, SIMDLoadOp::LoadSplatVec32x4)"),
("v128.load64_splat", "makeSIMDLoad(s, SIMDLoadOp::LoadSplatVec64x2)"),
("v128.load8_splat", "makeSIMDLoad(s, SIMDLoadOp::Load8SplatVec128)"),
("v128.load16_splat", "makeSIMDLoad(s, SIMDLoadOp::Load16SplatVec128)"),
("v128.load32_splat", "makeSIMDLoad(s, SIMDLoadOp::Load32SplatVec128)"),
("v128.load64_splat", "makeSIMDLoad(s, SIMDLoadOp::Load64SplatVec128)"),
("v128.load8x8_s", "makeSIMDLoad(s, SIMDLoadOp::LoadExtSVec8x8ToVecI16x8)"),
("v128.load8x8_u", "makeSIMDLoad(s, SIMDLoadOp::LoadExtUVec8x8ToVecI16x8)"),
("v128.load16x4_s", "makeSIMDLoad(s, SIMDLoadOp::LoadExtSVec16x4ToVecI32x4)"),
("v128.load16x4_u", "makeSIMDLoad(s, SIMDLoadOp::LoadExtUVec16x4ToVecI32x4)"),
("v128.load32x2_s", "makeSIMDLoad(s, SIMDLoadOp::LoadExtSVec32x2ToVecI64x2)"),
("v128.load32x2_u", "makeSIMDLoad(s, SIMDLoadOp::LoadExtUVec32x2ToVecI64x2)"),
("v128.load32_zero", "makeSIMDLoad(s, SIMDLoadOp::Load32Zero)"),
("v128.load64_zero", "makeSIMDLoad(s, SIMDLoadOp::Load64Zero)"),
("v128.load32_zero", "makeSIMDLoad(s, SIMDLoadOp::Load32ZeroVec128)"),
("v128.load64_zero", "makeSIMDLoad(s, SIMDLoadOp::Load64ZeroVec128)"),
("i8x16.narrow_i16x8_s", "makeBinary(s, BinaryOp::NarrowSVecI16x8ToVecI8x16)"),
("i8x16.narrow_i16x8_u", "makeBinary(s, BinaryOp::NarrowUVecI16x8ToVecI8x16)"),
("i16x8.narrow_i32x4_s", "makeBinary(s, BinaryOp::NarrowSVecI32x4ToVecI16x8)"),
Expand Down
12 changes: 6 additions & 6 deletions src/binaryen-c.cpp
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Expand Up @@ -665,10 +665,10 @@ BinaryenOp BinaryenConvertSVecI32x4ToVecF32x4(void) {
BinaryenOp BinaryenConvertUVecI32x4ToVecF32x4(void) {
return ConvertUVecI32x4ToVecF32x4;
}
BinaryenOp BinaryenLoadSplatVec8x16(void) { return LoadSplatVec8x16; }
BinaryenOp BinaryenLoadSplatVec16x8(void) { return LoadSplatVec16x8; }
BinaryenOp BinaryenLoadSplatVec32x4(void) { return LoadSplatVec32x4; }
BinaryenOp BinaryenLoadSplatVec64x2(void) { return LoadSplatVec64x2; }
BinaryenOp BinaryenLoad8SplatVec128(void) { return Load8SplatVec128; }
BinaryenOp BinaryenLoad16SplatVec128(void) { return Load16SplatVec128; }
BinaryenOp BinaryenLoad32SplatVec128(void) { return Load32SplatVec128; }
BinaryenOp BinaryenLoad64SplatVec128(void) { return Load64SplatVec128; }
BinaryenOp BinaryenLoadExtSVec8x8ToVecI16x8(void) {
return LoadExtSVec8x8ToVecI16x8;
}
Expand All @@ -687,8 +687,8 @@ BinaryenOp BinaryenLoadExtSVec32x2ToVecI64x2(void) {
BinaryenOp BinaryenLoadExtUVec32x2ToVecI64x2(void) {
return LoadExtUVec32x2ToVecI64x2;
}
BinaryenOp BinaryenLoad32Zero(void) { return Load32Zero; }
BinaryenOp BinaryenLoad64Zero(void) { return Load64Zero; }
BinaryenOp BinaryenLoad32ZeroVec128(void) { return Load32ZeroVec128; }
BinaryenOp BinaryenLoad64ZeroVec128(void) { return Load64ZeroVec128; }
BinaryenOp BinaryenLoad8LaneVec128(void) { return Load8LaneVec128; }
BinaryenOp BinaryenLoad16LaneVec128(void) { return Load16LaneVec128; }
BinaryenOp BinaryenLoad32LaneVec128(void) { return Load32LaneVec128; }
Expand Down
12 changes: 6 additions & 6 deletions src/binaryen-c.h
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Expand Up @@ -548,18 +548,18 @@ BINARYEN_API BinaryenOp BinaryenTruncSatSVecF32x4ToVecI32x4(void);
BINARYEN_API BinaryenOp BinaryenTruncSatUVecF32x4ToVecI32x4(void);
BINARYEN_API BinaryenOp BinaryenConvertSVecI32x4ToVecF32x4(void);
BINARYEN_API BinaryenOp BinaryenConvertUVecI32x4ToVecF32x4(void);
BINARYEN_API BinaryenOp BinaryenLoadSplatVec8x16(void);
BINARYEN_API BinaryenOp BinaryenLoadSplatVec16x8(void);
BINARYEN_API BinaryenOp BinaryenLoadSplatVec32x4(void);
BINARYEN_API BinaryenOp BinaryenLoadSplatVec64x2(void);
BINARYEN_API BinaryenOp BinaryenLoad8SplatVec128(void);
BINARYEN_API BinaryenOp BinaryenLoad16SplatVec128(void);
BINARYEN_API BinaryenOp BinaryenLoad32SplatVec128(void);
BINARYEN_API BinaryenOp BinaryenLoad64SplatVec128(void);
BINARYEN_API BinaryenOp BinaryenLoadExtSVec8x8ToVecI16x8(void);
BINARYEN_API BinaryenOp BinaryenLoadExtUVec8x8ToVecI16x8(void);
BINARYEN_API BinaryenOp BinaryenLoadExtSVec16x4ToVecI32x4(void);
BINARYEN_API BinaryenOp BinaryenLoadExtUVec16x4ToVecI32x4(void);
BINARYEN_API BinaryenOp BinaryenLoadExtSVec32x2ToVecI64x2(void);
BINARYEN_API BinaryenOp BinaryenLoadExtUVec32x2ToVecI64x2(void);
BINARYEN_API BinaryenOp BinaryenLoad32Zero(void);
BINARYEN_API BinaryenOp BinaryenLoad64Zero(void);
BINARYEN_API BinaryenOp BinaryenLoad32ZeroVec128(void);
BINARYEN_API BinaryenOp BinaryenLoad64ZeroVec128(void);
BINARYEN_API BinaryenOp BinaryenLoad8LaneVec128(void);
BINARYEN_API BinaryenOp BinaryenLoad16LaneVec128(void);
BINARYEN_API BinaryenOp BinaryenLoad32LaneVec128(void);
Expand Down
12 changes: 6 additions & 6 deletions src/gen-s-parser.inc
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Expand Up @@ -3001,7 +3001,7 @@ switch (op[0]) {
if (strcmp(op, "v128.load16_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load16LaneVec128); }
goto parse_error;
case 's':
if (strcmp(op, "v128.load16_splat") == 0) { return makeSIMDLoad(s, SIMDLoadOp::LoadSplatVec16x8); }
if (strcmp(op, "v128.load16_splat") == 0) { return makeSIMDLoad(s, SIMDLoadOp::Load16SplatVec128); }
goto parse_error;
default: goto parse_error;
}
Expand All @@ -3028,10 +3028,10 @@ switch (op[0]) {
if (strcmp(op, "v128.load32_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load32LaneVec128); }
goto parse_error;
case 's':
if (strcmp(op, "v128.load32_splat") == 0) { return makeSIMDLoad(s, SIMDLoadOp::LoadSplatVec32x4); }
if (strcmp(op, "v128.load32_splat") == 0) { return makeSIMDLoad(s, SIMDLoadOp::Load32SplatVec128); }
goto parse_error;
case 'z':
if (strcmp(op, "v128.load32_zero") == 0) { return makeSIMDLoad(s, SIMDLoadOp::Load32Zero); }
if (strcmp(op, "v128.load32_zero") == 0) { return makeSIMDLoad(s, SIMDLoadOp::Load32ZeroVec128); }
goto parse_error;
default: goto parse_error;
}
Expand All @@ -3056,10 +3056,10 @@ switch (op[0]) {
if (strcmp(op, "v128.load64_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load64LaneVec128); }
goto parse_error;
case 's':
if (strcmp(op, "v128.load64_splat") == 0) { return makeSIMDLoad(s, SIMDLoadOp::LoadSplatVec64x2); }
if (strcmp(op, "v128.load64_splat") == 0) { return makeSIMDLoad(s, SIMDLoadOp::Load64SplatVec128); }
goto parse_error;
case 'z':
if (strcmp(op, "v128.load64_zero") == 0) { return makeSIMDLoad(s, SIMDLoadOp::Load64Zero); }
if (strcmp(op, "v128.load64_zero") == 0) { return makeSIMDLoad(s, SIMDLoadOp::Load64ZeroVec128); }
goto parse_error;
default: goto parse_error;
}
Expand All @@ -3072,7 +3072,7 @@ switch (op[0]) {
if (strcmp(op, "v128.load8_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load8LaneVec128); }
goto parse_error;
case 's':
if (strcmp(op, "v128.load8_splat") == 0) { return makeSIMDLoad(s, SIMDLoadOp::LoadSplatVec8x16); }
if (strcmp(op, "v128.load8_splat") == 0) { return makeSIMDLoad(s, SIMDLoadOp::Load8SplatVec128); }
goto parse_error;
default: goto parse_error;
}
Expand Down
24 changes: 12 additions & 12 deletions src/js/binaryen.js-post.js
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Expand Up @@ -480,18 +480,18 @@ function initializeConstants() {
'TruncSatUVecF32x4ToVecI32x4',
'ConvertSVecI32x4ToVecF32x4',
'ConvertUVecI32x4ToVecF32x4',
'LoadSplatVec8x16',
'LoadSplatVec16x8',
'LoadSplatVec32x4',
'LoadSplatVec64x2',
'Load8SplatVec128',
'Load16SplatVec128',
'Load32SplatVec128',
'Load64SplatVec128',
'LoadExtSVec8x8ToVecI16x8',
'LoadExtUVec8x8ToVecI16x8',
'LoadExtSVec16x4ToVecI32x4',
'LoadExtUVec16x4ToVecI32x4',
'LoadExtSVec32x2ToVecI64x2',
'LoadExtUVec32x2ToVecI64x2',
'Load32Zero',
'Load64Zero',
'Load32ZeroVec128',
'Load64ZeroVec128',
'Load8LaneVec128',
'Load16LaneVec128',
'Load32LaneVec128',
Expand Down Expand Up @@ -1471,16 +1471,16 @@ function wrapModule(module, self = {}) {
return Module['_BinaryenLoad'](module, 16, false, offset, align, Module['v128'], ptr);
},
'load8_splat'(offset, align, ptr) {
return Module['_BinaryenSIMDLoad'](module, Module['LoadSplatVec8x16'], offset, align, ptr);
return Module['_BinaryenSIMDLoad'](module, Module['Load8SplatVec128'], offset, align, ptr);
},
'load16_splat'(offset, align, ptr) {
return Module['_BinaryenSIMDLoad'](module, Module['LoadSplatVec16x8'], offset, align, ptr);
return Module['_BinaryenSIMDLoad'](module, Module['Load16SplatVec128'], offset, align, ptr);
},
'load32_splat'(offset, align, ptr) {
return Module['_BinaryenSIMDLoad'](module, Module['LoadSplatVec32x4'], offset, align, ptr);
return Module['_BinaryenSIMDLoad'](module, Module['Load32SplatVec128'], offset, align, ptr);
},
'load64_splat'(offset, align, ptr) {
return Module['_BinaryenSIMDLoad'](module, Module['LoadSplatVec64x2'], offset, align, ptr);
return Module['_BinaryenSIMDLoad'](module, Module['Load64SplatVec128'], offset, align, ptr);
},
'load8x8_s'(offset, align, ptr) {
return Module['_BinaryenSIMDLoad'](module, Module['LoadExtSVec8x8ToVecI16x8'], offset, align, ptr);
Expand All @@ -1501,10 +1501,10 @@ function wrapModule(module, self = {}) {
return Module['_BinaryenSIMDLoad'](module, Module['LoadExtUVec32x2ToVecI64x2'], offset, align, ptr);
},
'load32_zero'(offset, align, ptr) {
return Module['_BinaryenSIMDLoad'](module, Module['Load32Zero'], offset, align, ptr);
return Module['_BinaryenSIMDLoad'](module, Module['Load32ZeroVec128'], offset, align, ptr);
},
'load64_zero'(offset, align, ptr) {
return Module['_BinaryenSIMDLoad'](module, Module['Load64Zero'], offset, align, ptr);
return Module['_BinaryenSIMDLoad'](module, Module['Load64ZeroVec128'], offset, align, ptr);
},
'load8_lane'(offset, align, index, ptr, vec) {
return Module['_BinaryenSIMDLoadStoreLane'](module, Module['Load8LaneVec128'], offset, align, index, ptr, vec);
Expand Down
12 changes: 6 additions & 6 deletions src/passes/Print.cpp
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Expand Up @@ -699,16 +699,16 @@ struct PrintExpressionContents
void visitSIMDLoad(SIMDLoad* curr) {
prepareColor(o);
switch (curr->op) {
case LoadSplatVec8x16:
case Load8SplatVec128:
o << "v128.load8_splat";
break;
case LoadSplatVec16x8:
case Load16SplatVec128:
o << "v128.load16_splat";
break;
case LoadSplatVec32x4:
case Load32SplatVec128:
o << "v128.load32_splat";
break;
case LoadSplatVec64x2:
case Load64SplatVec128:
o << "v128.load64_splat";
break;
case LoadExtSVec8x8ToVecI16x8:
Expand All @@ -729,10 +729,10 @@ struct PrintExpressionContents
case LoadExtUVec32x2ToVecI64x2:
o << "v128.load32x2_u";
break;
case Load32Zero:
case Load32ZeroVec128:
o << "v128.load32_zero";
break;
case Load64Zero:
case Load64ZeroVec128:
o << "v128.load64_zero";
break;
}
Expand Down
20 changes: 10 additions & 10 deletions src/tools/fuzzing.h
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Expand Up @@ -2946,10 +2946,10 @@ class TranslateToFuzzReader {

Expression* makeSIMDLoad() {
// TODO: add Load{32,64}Zero if merged to proposal
SIMDLoadOp op = pick(LoadSplatVec8x16,
LoadSplatVec16x8,
LoadSplatVec32x4,
LoadSplatVec64x2,
SIMDLoadOp op = pick(Load8SplatVec128,
Load16SplatVec128,
Load32SplatVec128,
Load64SplatVec128,
LoadExtSVec8x8ToVecI16x8,
LoadExtUVec8x8ToVecI16x8,
LoadExtSVec16x4ToVecI32x4,
Expand All @@ -2959,16 +2959,16 @@ class TranslateToFuzzReader {
Address offset = logify(get());
Address align;
switch (op) {
case LoadSplatVec8x16:
case Load8SplatVec128:
align = 1;
break;
case LoadSplatVec16x8:
case Load16SplatVec128:
align = pick(1, 2);
break;
case LoadSplatVec32x4:
case Load32SplatVec128:
align = pick(1, 2, 4);
break;
case LoadSplatVec64x2:
case Load64SplatVec128:
case LoadExtSVec8x8ToVecI16x8:
case LoadExtUVec8x8ToVecI16x8:
case LoadExtSVec16x4ToVecI32x4:
Expand All @@ -2977,8 +2977,8 @@ class TranslateToFuzzReader {
case LoadExtUVec32x2ToVecI64x2:
align = pick(1, 2, 4, 8);
break;
case Load32Zero:
case Load64Zero:
case Load32ZeroVec128:
case Load64ZeroVec128:
WASM_UNREACHABLE("Unexpected SIMD loads");
}
Expression* ptr = makePointer();
Expand Down
24 changes: 12 additions & 12 deletions src/wasm-interpreter.h
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Expand Up @@ -2681,10 +2681,10 @@ template<typename GlobalManager, typename SubType> class ModuleInstanceBase {
Flow visitSIMDLoad(SIMDLoad* curr) {
NOTE_ENTER("SIMDLoad");
switch (curr->op) {
case LoadSplatVec8x16:
case LoadSplatVec16x8:
case LoadSplatVec32x4:
case LoadSplatVec64x2:
case Load8SplatVec128:
case Load16SplatVec128:
case Load32SplatVec128:
case Load64SplatVec128:
return visitSIMDLoadSplat(curr);
case LoadExtSVec8x8ToVecI16x8:
case LoadExtUVec8x8ToVecI16x8:
Expand All @@ -2693,8 +2693,8 @@ template<typename GlobalManager, typename SubType> class ModuleInstanceBase {
case LoadExtSVec32x2ToVecI64x2:
case LoadExtUVec32x2ToVecI64x2:
return visitSIMDLoadExtend(curr);
case Load32Zero:
case Load64Zero:
case Load32ZeroVec128:
case Load64ZeroVec128:
return visitSIMDLoadZero(curr);
}
WASM_UNREACHABLE("invalid op");
Expand All @@ -2710,16 +2710,16 @@ template<typename GlobalManager, typename SubType> class ModuleInstanceBase {
load.ptr = curr->ptr;
Literal (Literal::*splat)() const = nullptr;
switch (curr->op) {
case LoadSplatVec8x16:
case Load8SplatVec128:
splat = &Literal::splatI8x16;
break;
case LoadSplatVec16x8:
case Load16SplatVec128:
splat = &Literal::splatI16x8;
break;
case LoadSplatVec32x4:
case Load32SplatVec128:
splat = &Literal::splatI32x4;
break;
case LoadSplatVec64x2:
case Load64SplatVec128:
load.type = Type::i64;
splat = &Literal::splatI64x2;
break;
Expand Down Expand Up @@ -2797,8 +2797,8 @@ template<typename GlobalManager, typename SubType> class ModuleInstanceBase {
Address src = instance.getFinalAddress(
curr, flow.getSingleValue(), curr->getMemBytes());
auto zero =
Literal::makeZero(curr->op == Load32Zero ? Type::i32 : Type::i64);
if (curr->op == Load32Zero) {
Literal::makeZero(curr->op == Load32ZeroVec128 ? Type::i32 : Type::i64);
if (curr->op == Load32ZeroVec128) {
auto val = Literal(instance.externalInterface->load32u(src));
return Literal(std::array<Literal, 4>{{val, zero, zero, zero}});
} else {
Expand Down
12 changes: 6 additions & 6 deletions src/wasm.h
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Expand Up @@ -500,18 +500,18 @@ enum SIMDShiftOp {
};

enum SIMDLoadOp {
LoadSplatVec8x16,
LoadSplatVec16x8,
LoadSplatVec32x4,
LoadSplatVec64x2,
Load8SplatVec128,
Load16SplatVec128,
Load32SplatVec128,
Load64SplatVec128,
LoadExtSVec8x8ToVecI16x8,
LoadExtUVec8x8ToVecI16x8,
LoadExtSVec16x4ToVecI32x4,
LoadExtUVec16x4ToVecI32x4,
LoadExtSVec32x2ToVecI64x2,
LoadExtUVec32x2ToVecI64x2,
Load32Zero,
Load64Zero,
Load32ZeroVec128,
Load64ZeroVec128,
};

enum SIMDLoadStoreLaneOp {
Expand Down
12 changes: 6 additions & 6 deletions src/wasm/wasm-binary.cpp
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Expand Up @@ -5834,19 +5834,19 @@ bool WasmBinaryBuilder::maybeVisitSIMDLoad(Expression*& out, uint32_t code) {
switch (code) {
case BinaryConsts::V8x16LoadSplat:
curr = allocator.alloc<SIMDLoad>();
curr->op = LoadSplatVec8x16;
curr->op = Load8SplatVec128;
break;
case BinaryConsts::V16x8LoadSplat:
curr = allocator.alloc<SIMDLoad>();
curr->op = LoadSplatVec16x8;
curr->op = Load16SplatVec128;
break;
case BinaryConsts::V32x4LoadSplat:
curr = allocator.alloc<SIMDLoad>();
curr->op = LoadSplatVec32x4;
curr->op = Load32SplatVec128;
break;
case BinaryConsts::V64x2LoadSplat:
curr = allocator.alloc<SIMDLoad>();
curr->op = LoadSplatVec64x2;
curr->op = Load64SplatVec128;
break;
case BinaryConsts::I16x8LoadExtSVec8x8:
curr = allocator.alloc<SIMDLoad>();
Expand Down Expand Up @@ -5874,11 +5874,11 @@ bool WasmBinaryBuilder::maybeVisitSIMDLoad(Expression*& out, uint32_t code) {
break;
case BinaryConsts::V128Load32Zero:
curr = allocator.alloc<SIMDLoad>();
curr->op = Load32Zero;
curr->op = Load32ZeroVec128;
break;
case BinaryConsts::V128Load64Zero:
curr = allocator.alloc<SIMDLoad>();
curr->op = Load64Zero;
curr->op = Load64ZeroVec128;
break;
default:
return false;
Expand Down
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