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[SYCL] Add more details about the -fintelfpga option #1218

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Merged
merged 1 commit into from
Mar 3, 2020
Merged

[SYCL] Add more details about the -fintelfpga option #1218

merged 1 commit into from
Mar 3, 2020

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fwyzard
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@fwyzard fwyzard commented Feb 28, 2020

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@fwyzard fwyzard mentioned this pull request Feb 28, 2020
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MrSidims
MrSidims approved these changes Mar 3, 2020
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Thanks!

@bader bader merged commit 4b03ddb into intel:sycl Mar 3, 2020
alexbatashev pushed a commit to alexbatashev/llvm that referenced this pull request Mar 4, 2020
Merge remote-tracking branch 'origin/sycl' into private/abatashe/refa…
3749455 
…ctor_tests

* origin/sycl: (32 commits)
  [SYCL] Fix circular reference between events and queues (intel#1226)
  [CI][Doc] Use SSH to deploy GitHub Pages (intel#1232)
  [SYCL][CUDA][Test] Testing for use of CUDA primary context (intel#1174)
  [SYCL] allow underscore symbol in temporary directory name
  [SYCL] Reject zero length arrays (intel#1153)
  [SYCL] Fix static code analyzis concerns (intel#1189)
  [SYCL] Add more details about the -fintelfpga option (intel#1218)
  [SYCL][CUDA] Select only NVPTX64 device binaries (intel#1223)
  [SYCL] Reverse max work-group size order (intel#1177)
  [SYCL][Doc] Add GroupAlgorithms extension (intel#1079)
  [SYCL] Fix SYCL internal enumerators conflict with user defined macro (intel#1188)
  [SYCL][CUDA] Fixes context release and unnamed context scope (intel#1207)
  [SYCL][CUDA] Fix context creation property parsing
  [CUDA][PI] clang-format pi.h
  [SYCL][CUDA] Handle the case of not having any CUDA device (intel#1212)
  [SYCL] Fix check-sycl-deploy target problems (intel#1165)
  [SYCL] Disable tests which take more than 5 minutes (intel#1220)
  [SYCL] Make context constructors explicit to avoid unintended conversions (intel#1219)
  [SYCL][NFC] Add clang-format configuration file for SYCL LIT tests (intel#1224)
  [SYCL] Fix command cleanup invoked from multiple threads (intel#1214)
  ...
alexbatashev pushed a commit to alexbatashev/llvm that referenced this pull request Mar 5, 2020
Merge remote-tracking branch 'origin/sycl' into private/abatashe/host…
71cbcf6 
…_accessor_refactor

* origin/sycl: (38 commits)
  [SYCL] Fix device::get_devices() with a non-host device type (intel#1235)
  [SYCL][PI][CUDA] Implement kernel and kernel-group information queries (intel#1180)
  [SYCL] Remove default error code value in exception (intel#1150)
  [SYCL] Fix devicelib assert LIT test (intel#1245)
  [SYCL] Set aux-target-cpu for SYCL offload device compilation (intel#1225)
  [SYCL] Remove fabs and ceil from the list of unsupported math functions (intel#1217)
  [SYCL] Fix circular reference between events and queues (intel#1226)
  [CI][Doc] Use SSH to deploy GitHub Pages (intel#1232)
  [SYCL][CUDA][Test] Testing for use of CUDA primary context (intel#1174)
  [SYCL] allow underscore symbol in temporary directory name
  [SYCL] Reject zero length arrays (intel#1153)
  [SYCL] Fix static code analyzis concerns (intel#1189)
  [SYCL] Add more details about the -fintelfpga option (intel#1218)
  [SYCL][CUDA] Select only NVPTX64 device binaries (intel#1223)
  [SYCL] Reverse max work-group size order (intel#1177)
  [SYCL][Doc] Add GroupAlgorithms extension (intel#1079)
  [SYCL] Fix SYCL internal enumerators conflict with user defined macro (intel#1188)
  [SYCL][CUDA] Fixes context release and unnamed context scope (intel#1207)
  [SYCL][CUDA] Fix context creation property parsing
  [CUDA][PI] clang-format pi.h
  ...
@fwyzard fwyzard deleted the patch-1 branch March 11, 2020 21:43
FreddyLeaf pushed a commit to FreddyLeaf/llvm that referenced this pull request Mar 22, 2023
@tiwaria1 @FreddyLeaf
Implement RegisterMapInterfaceINTEL execution mode (intel#1774)
1b50431 
This PR adds the new execution mode RegisterMapInterfaceINTEL, see the Khronos
SPIRV spec here: KhronosGroup/SPIRV-Registry#176
This execution mode allows specifying a 'register' based interface for FPGA kernels.

The RegisterMapInterfaceINTEL execution mode is added with a 0/1 literal based on
the kernel metadata. When the metadata is:

!ip_interface !N
!N = !{!"csr"}
The translator emits RegisterMapInterfaceINTEL 0, and when the metadata is:

!ip_interface !N
!N = !{!"csr", !"accept_downstream_stall"}
The translator emits RegisterMapInterfaceINTEL 1

NOTE
The new mode is under capability FPGAKernelAttributesv2INTEL which implicitly defines the capability FPGAKernelAttributesv2INTEL.
This PR is very similar to Implement StreamingInterfaceINTEL execution mode intel#1218

Original commit:
KhronosGroup/SPIRV-LLVM-Translator@a9f4f25
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@GarveyJoe GarveyJoe GarveyJoe left review comments

@MrSidims MrSidims MrSidims approved these changes

@AGindinson AGindinson Awaiting requested review from AGindinson

@domiyan domiyan Awaiting requested review from domiyan

@mdtoguchi mdtoguchi Awaiting requested review from mdtoguchi

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4 participants
@fwyzard @MrSidims @GarveyJoe @bader