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[SYCL][FPGA] Enable a set of loop attributes #1312

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Merged
merged 4 commits into from
Mar 26, 2020

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vmaksimo
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This patch introduces the following loop attributes:

  • loop_coalesce:
    Indicates that the loop nest should be coalesced into a single loop without
    affecting functionality
  • speculated_iterations:
    Specifies the number of concurrent speculated iterations that will be in
    flight for a loop invocation
  • disable_loop_pipelining:
    Disables pipelining of the loop data path, causing the loop to be executed
    serially
  • max_interleaving:
    Places a maximum limit N on the number of interleaved invocations of an inner
    loop by an outer loop

Signed-off-by: Viktoria Maksimova [email protected]

This patch introduces the following loop attributes:
- loop_coalesce:
  Indicates that the loop nest should be coalesced into a single loop without
  affecting functionality
- speculated_iterations:
  Specifies the number of concurrent speculated iterations that will be in
  flight for a loop invocation
- disable_loop_pipelining:
  Disables pipelining of the loop data path, causing the loop to be executed
  serially
- max_interleaving:
  Places a maximum limit N on the number of interleaved invocations of an inner
  loop by an outer loop

Signed-off-by: Viktoria Maksimova <[email protected]>
Signed-off-by: Viktoria Maksimova <[email protected]>
@vmaksimo vmaksimo requested review from MrSidims and AGindinson March 13, 2020 15:26
Signed-off-by: Viktoria Maksimova <[email protected]>
@vmaksimo vmaksimo requested a review from MrSidims March 24, 2020 12:09
@AGindinson AGindinson assigned MrSidims and unassigned AGindinson Mar 24, 2020
Signed-off-by: Viktoria Maksimova <[email protected]>
@@ -364,7 +364,7 @@ int main() {
boo();
goo();
zoo();
woo();
loop_attrs_compatibility();
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Can't stop laughing on this test: "foo, boo, goo. zoo... loop_attrs_compatibility" :)

@MrSidims MrSidims self-requested a review March 26, 2020 10:59
@romanovvlad romanovvlad merged commit a5b9804 into intel:sycl Mar 26, 2020
alexbatashev added a commit to alexbatashev/llvm that referenced this pull request Mar 27, 2020
…hinx

* upstream/sycl: (357 commits)
  [Support] Implement a simple tabular data management library (intel#1358)
  [Support] Implement a property set I/O library (intel#1357)
  [SYCL] Fix buffer constructor using iterators (intel#1386)
  [SYCL][FPGA] Enable a set of loop attributes (intel#1312)
  [Driver][SYCL][FPGA] Proper dependency output location when given /Fo<dir> (intel#1346)
  [SPIR-V] Enabling SPIR-V builtin lookup in device SYCL mode (intel#1384)
  [SYCL][NFC] Unify setting kernel arguments (intel#1379)
  [SYCL][Doc] First revision of standard layout relaxation extension (intel#1344)
  [SYCL] Fixed sub-buffer alloca search (intel#1385)
  [SYCL][FPGA] Emit multiple IR variants for the IVDep attribute (intel#1383)
  [SYCL] Add experimental flag to enable front-end optimizations (intel#1376)
  [SYCL] Remove unexpected double in complex SPIR-V for float support (intel#1381)
  [SYCL] Default work-group sizes based on max (intel#952)
  [SYCL][CUDA] Fix usage of multiple backends in the same program (intel#1252)
  [SPIR-V] Add SPIR-V builtin definitions to the builtin lookup.
  [SPIR-V] Add macro definition when -fdeclare-spirv-builtins is activated
  [SYCL] Fix sycl_generic printing
  [SYCL] Support intel::reqd_work_group_size (intel#1328)
  [SYCL][NFC] Make the RT::PiPlugin object private (intel#1375)
  [SPIRV] Add convergent attribute to SPIR-V built-ins (intel#1373)
  ...
aelovikov-intel pushed a commit to aelovikov-intel/llvm that referenced this pull request Feb 23, 2023
…1312)

The esimd_test_utils.hpp file has been changed to provide a correct esimd_emulator selector and the library_loading.cpp has been changed to only check for esimd_emulator loading if the filter is set to esimd_emulator. This checks the functionality introduced in the following PR: intel#6870
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5 participants