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[SYCL][FPGA] Enable a set of loop attributes #1312

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Merged
merged 4 commits into from
Mar 26, 2020
Merged

[SYCL][FPGA] Enable a set of loop attributes #1312

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[SYCL][FPGA] Enable a set of loop attributes
vmaksimo Jan 27, 2020
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vmaksimo Mar 13, 2020
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vmaksimo Mar 24, 2020
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vmaksimo Mar 24, 2020
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2 changes: 2 additions & 0 deletions clang/lib/CodeGen/CGLoopInfo.cpp
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Expand Up @@ -535,6 +535,8 @@ MDNode *LoopInfo::createMetadata(
LoopProperties.push_back(MDNode::get(Ctx, Vals));
}

// disable_loop_pipelining attribute corresponds to
// 'llvm.loop.intel.pipelining.enable, i32 0' metadata
if (Attrs.SYCLLoopPipeliningDisable) {
Metadata *Vals[] = {MDString::get(Ctx, "llvm.loop.intel.pipelining.enable"),
ConstantAsMetadata::get(
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4 changes: 2 additions & 2 deletions clang/test/SemaSYCL/intel-fpga-loops.cpp
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Expand Up @@ -261,7 +261,7 @@ void zoo() {
}

// Test for Intel FPGA loop attributes compatibility
void woo() {
void loop_attrs_compatibility() {
int a[10];
// no diagnostics are expected
[[intelfpga::disable_loop_pipelining]]
Expand Down Expand Up @@ -364,7 +364,7 @@ int main() {
boo();
goo();
zoo();
woo();
loop_attrs_compatibility();
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Can't stop laughing on this test: "foo, boo, goo. zoo... loop_attrs_compatibility" :)

ivdep_dependent<4, 2, 1>();
//expected-note@-1 +{{in instantiation of function template specialization}}
ivdep_dependent<2, 4, -1>();
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