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Merged
merged 7 commits into from
Jul 11, 2024
Merged

Task sequence revert #14359

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b490110
Revert "[SYCL][E2E] Disable TaskSequence/* tests on Linux (#13080)"
aejjehint Jun 28, 2024
5b1fac2
Revert "[SYCL][FPGA] Implement task_sequence header, properties, and …
aejjehint Jun 28, 2024
9657dcd
Empty commit
aejjehint Jun 28, 2024
30a7a66
Update fpga_kernel_properties.hpp header
aejjehint Jul 3, 2024
665b683
Update aspect-related failures
aejjehint Jul 8, 2024
956da95
more update
aejjehint Jul 8, 2024
e780477
Remove extra default extension
aejjehint Jul 10, 2024
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5 changes: 0 additions & 5 deletions clang/lib/CodeGen/CodeGenTypes.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -711,11 +711,6 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
"__spv::__spirv_CooperativeMatrixKHR") {
ResultType = ConvertSPVCooperativeMatrixType(RD);
break;
} else if (RD && RD->getQualifiedNameAsString() ==
"__spv::__spirv_TaskSequenceINTEL") {
ResultType = llvm::TargetExtType::get(getLLVMContext(),
"spirv.TaskSequenceINTEL");
break;
}
}
}
Expand Down
1 change: 0 additions & 1 deletion clang/lib/Driver/ToolChains/Clang.cpp
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Expand Up @@ -10553,7 +10553,6 @@ static void getTripleBasedSPIRVTransOpts(Compilation &C,
",+SPV_INTEL_fpga_argument_interfaces"
",+SPV_INTEL_fpga_invocation_pipelining_attributes"
",+SPV_INTEL_fpga_latency_control"
",+SPV_INTEL_task_sequence"
",+SPV_KHR_shader_clock"
",+SPV_INTEL_bindless_images";
ExtArg = ExtArg + DefaultExtArg + INTELExtArg;
Expand Down
11 changes: 0 additions & 11 deletions clang/test/CodeGenSYCL/intel-task-sequence.cpp
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3 changes: 0 additions & 3 deletions clang/test/Driver/sycl-spirv-ext.c
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Expand Up @@ -47,7 +47,6 @@
// CHECK-DEFAULT-SAME:,+SPV_INTEL_fpga_argument_interfaces
// CHECK-DEFAULT-SAME:,+SPV_INTEL_fpga_invocation_pipelining_attributes
// CHECK-DEFAULT-SAME:,+SPV_INTEL_fpga_latency_control
// CHECK-DEFAULT-SAME:,+SPV_INTEL_task_sequence
// CHECK-DEFAULT-SAME:,+SPV_KHR_shader_clock
// CHECK-DEFAULT-SAME:,+SPV_INTEL_bindless_images
// CHECK-DEFAULT-SAME:,+SPV_INTEL_token_type
Expand Down Expand Up @@ -82,7 +81,6 @@
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_fpga_buffer_location
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_fpga_argument_interfaces
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_fpga_latency_control
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_task_sequence
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_usm_storage_classes
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_runtime_aligned
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_fpga_cluster_attributes,+SPV_INTEL_loop_fuse
Expand Down Expand Up @@ -114,7 +112,6 @@
// CHECK-CPU-SAME:,+SPV_INTEL_fpga_argument_interfaces
// CHECK-CPU-SAME:,+SPV_INTEL_fpga_invocation_pipelining_attributes
// CHECK-CPU-SAME:,+SPV_INTEL_fpga_latency_control
// CHECK-CPU-SAME:,+SPV_INTEL_task_sequence
// CHECK-CPU-SAME:,+SPV_INTEL_token_type
// CHECK-CPU-SAME:,+SPV_INTEL_bfloat16_conversion
// CHECK-CPU-SAME:,+SPV_INTEL_joint_matrix
Expand Down
5 changes: 2 additions & 3 deletions llvm/include/llvm/SYCLLowerIR/DeviceConfigFile.td
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Expand Up @@ -77,7 +77,6 @@ def AspectExt_intel_matrix : Aspect<"ext_intel_matrix">;
def AspectExt_oneapi_is_composite : Aspect<"ext_oneapi_is_composite">;
def AspectExt_oneapi_is_component : Aspect<"ext_oneapi_is_component">;
def AspectExt_oneapi_graph : Aspect<"ext_oneapi_graph">;
def AspectExt_intel_fpga_task_sequence : Aspect<"ext_intel_fpga_task_sequence">;
def AspectExt_oneapi_limited_graph : Aspect<"ext_oneapi_limited_graph">;
def AspectExt_oneapi_private_alloca : Aspect<"ext_oneapi_private_alloca">;
def AspectExt_oneapi_queue_profiling_tag : Aspect<"ext_oneapi_queue_profiling_tag">;
Expand Down Expand Up @@ -138,8 +137,8 @@ def : TargetInfo<"__TestAspectList",
AspectExt_oneapi_bindless_sampled_image_fetch_3d_usm, AspectExt_oneapi_bindless_sampled_image_fetch_3d,
AspectExt_intel_esimd,
AspectExt_oneapi_ballot_group, AspectExt_oneapi_fixed_size_group, AspectExt_oneapi_opportunistic_group,
AspectExt_oneapi_tangle_group, AspectExt_intel_matrix, AspectExt_oneapi_is_composite, AspectExt_oneapi_is_component,
AspectExt_oneapi_graph, AspectExt_intel_fpga_task_sequence, AspectExt_oneapi_limited_graph,
AspectExt_oneapi_tangle_group, AspectExt_intel_matrix, AspectExt_oneapi_is_composite, AspectExt_oneapi_is_component,
AspectExt_oneapi_graph, AspectExt_oneapi_limited_graph,
AspectExt_oneapi_private_alloca, AspectExt_oneapi_queue_profiling_tag, AspectExt_oneapi_virtual_mem, AspectExt_oneapi_cuda_cluster_group],
[]>;
// This definition serves the only purpose of testing whether the deprecated aspect list defined in here and in SYCL RT
Expand Down
16 changes: 0 additions & 16 deletions llvm/lib/SYCLLowerIR/CompileTimePropertiesPass.cpp
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Expand Up @@ -416,7 +416,6 @@ attributeToExecModeMetadata(const Attribute &Attr, Function &F) {

if (AttrKindStr == "sycl-streaming-interface") {
// generate either:
// !ip_interface !N
// !N = !{!"streaming"} or
// !N = !{!"streaming", !"stall_free_return"}
SmallVector<Metadata *, 2> MD;
Expand All @@ -429,7 +428,6 @@ attributeToExecModeMetadata(const Attribute &Attr, Function &F) {

if (AttrKindStr == "sycl-register-map-interface") {
// generate either:
// !ip_interface !N
// !N = !{!"csr"} or
// !N = !{!"csr", !"wait_for_done_write"}
SmallVector<Metadata *, 2> MD;
Expand All @@ -440,20 +438,6 @@ attributeToExecModeMetadata(const Attribute &Attr, Function &F) {
MDNode::get(Ctx, MD));
}

if (AttrKindStr == "sycl-fpga-cluster") {
// generate either:
// !stall_free !N
// !N = !{i32 1} or
// !stall_enable !N
// !N = !{i32 1}
std::string ClusterType =
getAttributeAsInteger<uint32_t>(Attr) ? "stall_enable" : "stall_free";
Metadata *ClusterMDArgs[] = {
ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(Ctx), 1))};
return std::pair<std::string, MDNode *>(ClusterType,
MDNode::get(Ctx, ClusterMDArgs));
}

if ((AttrKindStr == SYCL_REGISTER_ALLOC_MODE_ATTR ||
AttrKindStr == SYCL_GRF_SIZE_ATTR) &&
!llvm::esimd::isESIMD(F)) {
Expand Down
33 changes: 0 additions & 33 deletions llvm/test/SYCLLowerIR/CompileTimePropertiesPass/kernel-attributes/fpga-cluster.ll
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19 changes: 0 additions & 19 deletions sycl/include/CL/__spirv/spirv_ops.hpp
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Expand Up @@ -1300,25 +1300,6 @@ extern __DPCPP_SYCL_EXTERNAL
std::enable_if_t<std::is_integral_v<to> && std::is_unsigned_v<to>, to>
__spirv_ConvertPtrToU(from val) noexcept;

template <typename RetT, typename... ArgsT>
extern __DPCPP_SYCL_EXTERNAL __spv::__spirv_TaskSequenceINTEL *
__spirv_TaskSequenceCreateINTEL(RetT (*f)(ArgsT...), int Pipelined = -1,
int ClusterMode = -1,
unsigned int ResponseCapacity = 0,
unsigned int InvocationCapacity = 0) noexcept;

template <typename... ArgsT>
extern __DPCPP_SYCL_EXTERNAL void
__spirv_TaskSequenceAsyncINTEL(__spv::__spirv_TaskSequenceINTEL *TaskSequence,
ArgsT... Args) noexcept;

template <typename RetT>
extern __DPCPP_SYCL_EXTERNAL RetT __spirv_TaskSequenceGetINTEL(
__spv::__spirv_TaskSequenceINTEL *TaskSequence) noexcept;

extern __DPCPP_SYCL_EXTERNAL void __spirv_TaskSequenceReleaseINTEL(
__spv::__spirv_TaskSequenceINTEL *TaskSequence) noexcept;

#else // if !__SYCL_DEVICE_ONLY__

template <typename dataT>
Expand Down
2 changes: 0 additions & 2 deletions sycl/include/CL/__spirv/spirv_types.hpp
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Expand Up @@ -123,8 +123,6 @@ template <typename T, std::size_t R, std::size_t C, MatrixLayout L,
MatrixUse U = MatrixUse::MatrixA>
struct __spirv_JointMatrixINTEL;

struct __spirv_TaskSequenceINTEL;

} // namespace __spv

#ifdef __SYCL_DEVICE_ONLY__
Expand Down
36 changes: 13 additions & 23 deletions sycl/include/sycl/device_aspect_macros.hpp
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Expand Up @@ -313,76 +313,71 @@
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_graph__ 0
#endif

#ifndef __SYCL_ALL_DEVICES_HAVE_ext_intel_fpga_task_sequence__
// __SYCL_ASPECT(ext_intel_fpga_task_sequence, 62)
#define __SYCL_ALL_DEVICES_HAVE_ext_intel_fpga_task_sequence__ 0
#endif

#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_limited_graph__
// __SYCL_ASPECT(ext_oneapi_limited_graph, 63)
// __SYCL_ASPECT(ext_oneapi_limited_graph, 62)
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_limited_graph__ 0
#endif

#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_private_alloca__
// __SYCL_ASPECT(ext_oneapi_private_alloca, 64)
// __SYCL_ASPECT(ext_oneapi_private_alloca, 63)
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_private_alloca__ 0
#endif

#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_cubemap__
// __SYCL_ASPECT(ext_oneapi_cubemap, 65)
// __SYCL_ASPECT(ext_oneapi_cubemap, 64)
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_cubemap__ 0
#endif

#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_cubemap_seamless_filtering__
// __SYCL_ASPECT(ext_oneapi_cubemap_seamless_filtering, 66)
// __SYCL_ASPECT(ext_oneapi_cubemap_seamless_filtering, 65)
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_cubemap_seamless_filtering__ 0
#endif

#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_1d_usm__
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_1d_usm, 67)
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_1d_usm, 66)
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_1d_usm__ \
0
#endif

#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_1d__
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_1d, 68)
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_1d, 67)
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_1d__ 0
#endif

#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_2d_usm__
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_2d_usm, 69)
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_2d_usm, 68)
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_2d_usm__ \
0
#endif

#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_2d__
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_2d, 70)
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_2d, 69)
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_2d__ 0
#endif

#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_3d_usm__
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_3d_usm, 71)
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_3d_usm, 70)
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_3d_usm__ \
0
#endif

#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_3d__
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_3d, 72)
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_3d, 71)
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_3d__ 0
#endif

#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_queue_profiling_tag__
// __SYCL_ASPECT(ext_oneapi_queue_profiling_tag, 73)
// __SYCL_ASPECT(ext_oneapi_queue_profiling_tag, 72)
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_queue_profiling_tag__ 0
#endif

#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_virtual_mem__
// __SYCL_ASPECT(ext_oneapi_virtual_mem, 74)
// __SYCL_ASPECT(ext_oneapi_virtual_mem, 73)
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_virtual_mem__ 0
#endif

#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_cuda_cluster_group__
// __SYCL_ASPECT(ext_oneapi_cuda_cluster_group, 75)
// __SYCL_ASPECT(ext_oneapi_cuda_cluster_group, 74)
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_cuda_cluster_group__ 0
#endif

Expand Down Expand Up @@ -691,11 +686,6 @@
#define __SYCL_ANY_DEVICE_HAS_ext_oneapi_graph__ 0
#endif

#ifndef __SYCL_ANY_DEVICE_HAS_ext_intel_fpga_task_sequence__
// __SYCL_ASPECT(ext_intel_fpga_task_sequence__, 62)
#define __SYCL_ANY_DEVICE_HAS_ext_intel_fpga_task_sequence__ 0
#endif

#ifndef __SYCL_ANY_DEVICE_HAS_ext_oneapi_limited_graph__
// __SYCL_ASPECT(ext_oneapi_limited_graph, 63)
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This and the following defines should all have been updated, similar to ALL_DEVICE_HAS.

The ID specified for ext_oneapi_limited_graph now does not match the ID defined in aspects.def anymore. The same applies for all following defines.

@aejjehint Can you please fix this in a follow-up PR?

#define __SYCL_ANY_DEVICE_HAS_ext_oneapi_limited_graph__ 0
Expand Down
62 changes: 4 additions & 58 deletions sycl/include/sycl/ext/intel/experimental/fpga_kernel_properties.hpp
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
//===--------------------- fpga_kernel_properties.hpp ---------------------===//
// SYCL properties associated with FPGA kernel properties
//==----- fpga_kernel_properties.hpp - SYCL properties associated with FPGA
// kernel properties ---==//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
Expand All @@ -12,31 +12,22 @@
#include <sycl/ext/oneapi/properties/property.hpp>
#include <sycl/ext/oneapi/properties/property_value.hpp>

#include <cstdint> // for uint16_t
#include <type_traits> // for true_type

namespace sycl {
inline namespace _V1 {
namespace ext::intel::experimental {

template <typename T, typename PropertyListT> class fpga_kernel_attribute;
template <auto &f, typename PropertyListT> class task_sequence;

enum class streaming_interface_options_enum : std::uint16_t {
enum class streaming_interface_options_enum : uint16_t {
accept_downstream_stall,
remove_downstream_stall
};

enum class register_map_interface_options_enum : std::uint16_t {
enum class register_map_interface_options_enum : uint16_t {
do_not_wait_for_done_write,
wait_for_done_write,
};

enum class fpga_cluster_options_enum : std::uint16_t {
stall_free,
stall_enable
};

struct streaming_interface_key
: oneapi::experimental::detail::compile_time_property_key<
oneapi::experimental::detail::PropKind::StreamingInterface> {
Expand All @@ -63,15 +54,6 @@ struct pipelined_key : oneapi::experimental::detail::compile_time_property_key<
std::integral_constant<int, pipeline_directive_or_initiation_interval>>;
};

struct fpga_cluster_key
: oneapi::experimental::detail::compile_time_property_key<
oneapi::experimental::detail::PropKind::FPGACluster> {
template <fpga_cluster_options_enum option>
using value_t = ext::oneapi::experimental::property_value<
fpga_cluster_key,
std::integral_constant<fpga_cluster_options_enum, option>>;
};

template <streaming_interface_options_enum option =
streaming_interface_options_enum::accept_downstream_stall>
inline constexpr streaming_interface_key::value_t<option> streaming_interface;
Expand Down Expand Up @@ -102,18 +84,6 @@ inline constexpr pipelined_key::value_t<
pipeline_directive_or_initiation_interval>
pipelined;

template <fpga_cluster_options_enum option =
fpga_cluster_options_enum::stall_free>
inline constexpr fpga_cluster_key::value_t<option> fpga_cluster;

inline constexpr fpga_cluster_key::value_t<
fpga_cluster_options_enum::stall_free>
stall_free_clusters;

inline constexpr fpga_cluster_key::value_t<
fpga_cluster_options_enum::stall_enable>
stall_enable_clusters;

} // namespace ext::intel::experimental

namespace ext::oneapi::experimental {
Expand All @@ -133,22 +103,6 @@ struct is_property_key_of<
intel::experimental::fpga_kernel_attribute<T, PropertyListT>>
: std::true_type {};

template <typename T, typename PropertyListT>
struct is_property_key_of<
intel::experimental::fpga_cluster_key,
intel::experimental::fpga_kernel_attribute<T, PropertyListT>>
: std::true_type {};

template <auto &f, typename PropertyListT>
struct is_property_key_of<intel::experimental::pipelined_key,
intel::experimental::task_sequence<f, PropertyListT>>
: std::true_type {};

template <auto &f, typename PropertyListT>
struct is_property_key_of<intel::experimental::fpga_cluster_key,
intel::experimental::task_sequence<f, PropertyListT>>
: std::true_type {};

namespace detail {
template <intel::experimental::streaming_interface_options_enum Stall_Free>
struct PropertyMetaInfo<
Expand All @@ -170,14 +124,6 @@ struct PropertyMetaInfo<intel::experimental::pipelined_key::value_t<Value>> {
static constexpr int value = Value;
};

template <intel::experimental::fpga_cluster_options_enum ClusterType>
struct PropertyMetaInfo<
intel::experimental::fpga_cluster_key::value_t<ClusterType>> {
static constexpr const char *name = "sycl-fpga-cluster";
static constexpr intel::experimental::fpga_cluster_options_enum value =
ClusterType;
};

} // namespace detail
} // namespace ext::oneapi::experimental
} // namespace _V1
Expand Down
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