AMDGPU: Add amdgpu-agpr-alloc attribute to control AGPR allocation #128034
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@llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) ChangesThis provides a range to decide how to subdivide the vector register I want this primarily for testing agpr allocation behavior. We should Patch is 32.50 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/128034.diff 3 Files Affected:
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index d580be1eb8cfc..2e9311908d8c9 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -1702,6 +1702,22 @@ The AMDGPU backend supports the following LLVM IR attributes.
function which requires AGPRs is reached through any function marked
with this attribute.
+ "amdgpu-num-agpr"="min(,max)" Indicates a minimum and maximum range for the number of AGPRs to make
+ available to allocate. The values will be rounded up to the next multiple
+ of the allocation granularity (4). The minimum value is interpreted as the
+ minimum number of AGPRs the function will require to allocate. If only one
+ value is specified, it is interpreted as the minimum register budget.
+
+ The values may be ignored if satisfying it would violate other allocation
+ constraints.
+
+ The behavior is undefined if a function which requires more AGPRs than the
+ lower bound is reached through any function marked with a higher value of this
+ attribute. A minimum value of 0 indicates the function does not require
+ any AGPRs. A minimum of 0 is equivalent to "amdgpu-no-agpr".
+
+ This is only relevant on targets with AGPRs which support accum_offset (gfx90a+).
+
"amdgpu-hidden-argument" This attribute is used internally by the backend to mark function arguments
as hidden. Hidden arguments are managed by the compiler and are not part of
the explicit arguments supplied by the user.
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 71c720ed09b5f..e0fe96cae6e19 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -572,9 +572,10 @@ MCRegister SIRegisterInfo::reservedPrivateSegmentBufferReg(
std::pair<unsigned, unsigned>
SIRegisterInfo::getMaxNumVectorRegs(const MachineFunction &MF) const {
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
- unsigned MaxNumVGPRs = ST.getMaxNumVGPRs(MF);
- unsigned MaxNumAGPRs = MaxNumVGPRs;
- unsigned TotalNumVGPRs = AMDGPU::VGPR_32RegClass.getNumRegs();
+ const unsigned MaxVectorRegs = ST.getMaxNumVGPRs(MF);
+
+ unsigned MaxNumVGPRs = MaxVectorRegs;
+ unsigned MaxNumAGPRs = 0;
// On GFX90A, the number of VGPRs and AGPRs need not be equal. Theoretically,
// a wave may have up to 512 total vector registers combining together both
@@ -585,16 +586,49 @@ SIRegisterInfo::getMaxNumVectorRegs(const MachineFunction &MF) const {
// TODO: it shall be possible to estimate maximum AGPR/VGPR pressure and split
// register file accordingly.
if (ST.hasGFX90AInsts()) {
- if (MFI->usesAGPRs(MF)) {
- MaxNumVGPRs /= 2;
- MaxNumAGPRs = MaxNumVGPRs;
+ unsigned MinNumAGPRs = 0;
+ const unsigned TotalNumAGPRs = AMDGPU::AGPR_32RegClass.getNumRegs();
+ const unsigned TotalNumVGPRs = AMDGPU::VGPR_32RegClass.getNumRegs();
+
+ const std::pair<unsigned, unsigned> DefaultNumAGPR = {~0u, ~0u};
+
+ // TODO: Replace amdgpu-no-agpr with amdgpu-num-agpr=0
+ // TODO: Move this logic into subtarget on IR function
+ //
+ // TODO: The lower bound should probably force the number of required
+ // registers up, overriding amdgpu-waves-per-eu.
+ std::tie(MinNumAGPRs, MaxNumAGPRs) = AMDGPU::getIntegerPairAttribute(
+ MF.getFunction(), "amdgpu-num-agpr", DefaultNumAGPR,
+ /*OnlyFirstRequired=*/true);
+
+ if (MinNumAGPRs == DefaultNumAGPR.first) {
+ // Default to splitting half the registers if AGPRs are required.
+
+ if (MFI->usesAGPRs(MF))
+ MinNumAGPRs = MaxNumAGPRs = MaxVectorRegs / 2;
+ else
+ MinNumAGPRs = 0;
} else {
- if (MaxNumVGPRs > TotalNumVGPRs) {
- MaxNumAGPRs = MaxNumVGPRs - TotalNumVGPRs;
- MaxNumVGPRs = TotalNumVGPRs;
- } else
- MaxNumAGPRs = 0;
+ // Align to accum_offset's allocation granularity.
+ MinNumAGPRs = alignTo(MinNumAGPRs, 4);
+
+ MinNumAGPRs = std::min(MinNumAGPRs, TotalNumAGPRs);
}
+
+ // Clamp values to be inbounds of our limits, and ensure min <= max.
+
+ MaxNumAGPRs = std::min(std::max(MinNumAGPRs, MaxNumAGPRs), MaxVectorRegs);
+ MinNumAGPRs = std::min(std::min(MinNumAGPRs, TotalNumAGPRs), MaxNumAGPRs);
+
+ MaxNumVGPRs = std::min(MaxVectorRegs - MinNumAGPRs, TotalNumVGPRs);
+ MaxNumAGPRs = std::min(MaxVectorRegs - MaxNumVGPRs, MaxNumAGPRs);
+
+ assert(MaxNumVGPRs + MaxNumAGPRs <= MaxVectorRegs &&
+ MaxNumAGPRs <= TotalNumAGPRs && MaxNumVGPRs <= TotalNumVGPRs &&
+ "invalid register counts");
+ } else if (ST.hasMAIInsts()) {
+ // On gfx908 the number of AGPRs always equals the number of VGPRs.
+ MaxNumAGPRs = MaxNumVGPRs = MaxVectorRegs;
}
return std::pair(MaxNumVGPRs, MaxNumAGPRs);
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-num-agpr.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-num-agpr.ll
new file mode 100644
index 0000000000000..8cad42eae37cd
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-num-agpr.ll
@@ -0,0 +1,508 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -filetype=null %s 2>&1 | FileCheck --implicit-check-not=warning -check-prefix=WARN %s
+
+; Check the effect that amdgpu-num-agpr has on register reservations.
+;
+; Asm clobbers will print a warning when they clobber reserved
+; registers, and should be uniquely identified in the message from the
+; !srcloc values.
+
+; The occupancy target warnings should be a side effect of violating
+; the register budget with asm.
+
+; WARN: warning: inline asm clobber list contains reserved registers: a0 at line 1
+define amdgpu_kernel void @min_num_agpr_0_0__amdgpu_no_agpr() #0 {
+ call void asm sideeffect "; clobber $0","~{a0}"(), !srcloc !{i32 1}
+ ret void
+}
+
+attributes #0 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="0,0" "amdgpu-no-agpr" }
+
+; Check parse of single entry 0
+
+; WARN: warning: inline asm clobber list contains reserved registers: a0 at line 2
+define amdgpu_kernel void @min_num_agpr_0__amdgpu_no_agpr() #1 {
+ call void asm sideeffect "; clobber $0","~{a0}"(), !srcloc !{i32 2}
+ call void asm sideeffect "; clobber $0","~{v0}"(), !srcloc !{i32 2}
+ ret void
+}
+
+attributes #1 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="0" "amdgpu-no-agpr" }
+
+
+; Undefined use
+define amdgpu_kernel void @min_num_agpr_1_1__amdgpu_no_agpr() #2 {
+ call void asm sideeffect "; clobber $0","~{a0}"(), !srcloc !{i32 3}
+ ret void
+}
+
+attributes #2 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="1,1" "amdgpu-no-agpr" }
+
+; Check parse of single entry 4, interpreted as the minimum. Total budget is 64.
+; WARN: warning: <unknown>:0:0: failed to meet occupancy target given by 'amdgpu-waves-per-eu' in 'min_num_agpr_4__amdgpu_no_agpr': desired occupancy was 8, final occupancy is 7
+; WARN: warning: inline asm clobber list contains reserved registers: v60 at line 4
+define amdgpu_kernel void @min_num_agpr_4__amdgpu_no_agpr() #3 {
+ call void asm sideeffect "; clobber $0","~{a0}"(), !srcloc !{i32 4}
+ call void asm sideeffect "; clobber $0","~{a3}"(), !srcloc !{i32 4}
+ call void asm sideeffect "; clobber $0","~{v59}"(), !srcloc !{i32 4}
+ call void asm sideeffect "; clobber $0","~{v60}"(), !srcloc !{i32 4}
+ ret void
+}
+
+attributes #3 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="4" "amdgpu-no-agpr" }
+
+
+; Allocation granularity requires rounding this to use 4 AGPRs, so the
+; top 4 VGPRs are unavailable. The maximum agpr count is also padded
+; up to the minimum of 4
+
+; WARN: warning: <unknown>:0:0: failed to meet occupancy target given by 'amdgpu-waves-per-eu' in 'min_num_agpr_occ8_1_1': desired occupancy was 8, final occupancy is 7
+; WARN: warning: inline asm clobber list contains reserved registers: a4 at line 5
+; WARN: warning: inline asm clobber list contains reserved registers: v60 at line 5
+; WARN: warning: inline asm clobber list contains reserved registers: v63 at line 5
+define amdgpu_kernel void @min_num_agpr_occ8_1_1() #4 {
+ call void asm sideeffect "; clobber $0","~{a3}"(), !srcloc !{i32 5}
+ call void asm sideeffect "; clobber $0","~{a4}"(), !srcloc !{i32 5}
+ call void asm sideeffect "; clobber $0","~{v59}"(), !srcloc !{i32 5}
+ call void asm sideeffect "; clobber $0","~{v60}"(), !srcloc !{i32 5}
+ call void asm sideeffect "; clobber $0","~{v63}"(), !srcloc !{i32 5}
+ ret void
+}
+
+attributes #4 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="1,1" }
+
+
+; WARN: warning: <unknown>:0:0: failed to meet occupancy target given by 'amdgpu-waves-per-eu' in 'min_num_agpr_64_64__amdgpu_no_agpr': desired occupancy was 8, final occupancy is 7
+; WARN: warning: inline asm clobber list contains reserved registers: v0 at line 6
+define amdgpu_kernel void @min_num_agpr_64_64__amdgpu_no_agpr() #5 {
+ call void asm sideeffect "; clobber $0","~{a63}"(), !srcloc !{i32 6}
+ call void asm sideeffect "; clobber $0","~{v0}"(), !srcloc !{i32 6}
+ ret void
+}
+
+attributes #5 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="64,64" "amdgpu-no-agpr" }
+
+; No free VGPRs
+; WARN: warning: inline asm clobber list contains reserved registers: v0 at line 7
+define amdgpu_kernel void @min_num_agpr_64_64() #6 {
+ call void asm sideeffect "; clobber $0","~{v0}"(), !srcloc !{i32 7}
+ call void asm sideeffect "; clobber $0","~{a0}"(), !srcloc !{i32 7}
+ ret void
+}
+
+attributes #6 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="64,64" }
+
+; WARN: warning: <unknown>:0:0: failed to meet occupancy target given by 'amdgpu-waves-per-eu' in 'min_num_agpr_63_64': desired occupancy was 8, final occupancy is 7
+; WARN: warning: inline asm clobber list contains reserved registers: v0 at line 8
+; WARN: warning: inline asm clobber list contains reserved registers: v3 at line 8
+define amdgpu_kernel void @min_num_agpr_63_64() #7 {
+ call void asm sideeffect "; clobber $0","~{v0}"(), !srcloc !{i32 8}
+ call void asm sideeffect "; clobber $0","~{v3}"(), !srcloc !{i32 8}
+ call void asm sideeffect "; clobber $0","~{a59}"(), !srcloc !{i32 8}
+ call void asm sideeffect "; clobber $0","~{a60}"(), !srcloc !{i32 8}
+ call void asm sideeffect "; clobber $0","~{a0}"(), !srcloc !{i32 8}
+ ret void
+}
+
+attributes #7 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="63,64" }
+
+
+; No-op value.
+define amdgpu_kernel void @min_num_agpr_occ8_0_64() #8 {
+ call void asm sideeffect "; clobber $0","~{v0}"(), !srcloc !{i32 9}
+ call void asm sideeffect "; clobber $0","~{v59}"(), !srcloc !{i32 9}
+ ret void
+}
+
+attributes #8 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="0,64" }
+
+
+; Register budget 64
+; WARN: warning: <unknown>:0:0: failed to meet occupancy target given by 'amdgpu-waves-per-eu' in 'min_num_agpr_occ8_11_59': desired occupancy was 8, final occupancy is 7
+; WARN: warning: inline asm clobber list contains reserved registers: a12 at line 10
+; WARN: warning: inline asm clobber list contains reserved registers: v52 at line 10
+define amdgpu_kernel void @min_num_agpr_occ8_11_59() #9 {
+ call void asm sideeffect "; clobber $0","~{a11}"(), !srcloc !{i32 10}
+ call void asm sideeffect "; clobber $0","~{a12}"(), !srcloc !{i32 10}
+ call void asm sideeffect "; clobber $0","~{v51}"(), !srcloc !{i32 10}
+ call void asm sideeffect "; clobber $0","~{v52}"(), !srcloc !{i32 10}
+ ret void
+}
+
+attributes #9 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="11,59" }
+
+
+; WARN: warning: <unknown>:0:0: failed to meet occupancy target given by 'amdgpu-waves-per-eu' in 'min_num_agpr_occ8_12_59': desired occupancy was 8, final occupancy is 7
+; WARN: warning: inline asm clobber list contains reserved registers: a12 at line 11
+; WARN: warning: inline asm clobber list contains reserved registers: v52 at line 11
+define amdgpu_kernel void @min_num_agpr_occ8_12_59() #10 {
+ call void asm sideeffect "; clobber $0","~{a11}"(), !srcloc !{i32 11}
+ call void asm sideeffect "; clobber $0","~{a12}"(), !srcloc !{i32 11}
+ call void asm sideeffect "; clobber $0","~{v51}"(), !srcloc !{i32 11}
+ call void asm sideeffect "; clobber $0","~{v52}"(), !srcloc !{i32 11}
+ ret void
+}
+
+attributes #10 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="12,59" }
+
+
+; WARN: warning: <unknown>:0:0: failed to meet occupancy target given by 'amdgpu-waves-per-eu' in 'min_num_agpr_occ8_12_20': desired occupancy was 8, final occupancy is 7
+; WARN: warning: inline asm clobber list contains reserved registers: a12 at line 12
+; WARN: warning: inline asm clobber list contains reserved registers: v52 at line 12
+define amdgpu_kernel void @min_num_agpr_occ8_12_20() #11 {
+ call void asm sideeffect "; clobber $0","~{a11}"(), !srcloc !{i32 12}
+ call void asm sideeffect "; clobber $0","~{a12}"(), !srcloc !{i32 12}
+ call void asm sideeffect "; clobber $0","~{v51}"(), !srcloc !{i32 12}
+ call void asm sideeffect "; clobber $0","~{v52}"(), !srcloc !{i32 12}
+ ret void
+}
+
+attributes #11 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="12,20" }
+
+
+; WARN: warning: inline asm clobber list contains reserved registers: a20 at line 13
+define amdgpu_kernel void @min_num_agpr_occ1_12_20() #12 {
+ call void asm sideeffect "; clobber $0","~{a12}"(), !srcloc !{i32 13}
+ call void asm sideeffect "; clobber $0","~{a19}"(), !srcloc !{i32 13}
+ call void asm sideeffect "; clobber $0","~{a20}"(), !srcloc !{i32 13}
+ call void asm sideeffect "; clobber $0","~{v0}"(), !srcloc !{i32 13}
+ call void asm sideeffect "; clobber $0","~{v20}"(), !srcloc !{i32 13}
+ call void asm sideeffect "; clobber $0","~{v255}"(), !srcloc !{i32 13}
+ ret void
+}
+
+attributes #12 = { "amdgpu-waves-per-eu"="1,1" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="12,20" }
+
+; WARN: warning: inline asm clobber list contains reserved registers: a20 at line 14
+define amdgpu_kernel void @min_num_agpr_occ1_13_20() #13 {
+ call void asm sideeffect "; clobber $0","~{a11}"(), !srcloc !{i32 14}
+ call void asm sideeffect "; clobber $0","~{a12}"(), !srcloc !{i32 14}
+ call void asm sideeffect "; clobber $0","~{a13}"(), !srcloc !{i32 14}
+ call void asm sideeffect "; clobber $0","~{a19}"(), !srcloc !{i32 14}
+ call void asm sideeffect "; clobber $0","~{a20}"(), !srcloc !{i32 14}
+ call void asm sideeffect "; clobber $0","~{v51}"(), !srcloc !{i32 14}
+ call void asm sideeffect "; clobber $0","~{v20}"(), !srcloc !{i32 14}
+ call void asm sideeffect "; clobber $0","~{v255}"(), !srcloc !{i32 14}
+ ret void
+}
+
+attributes #13 = { "amdgpu-waves-per-eu"="1,1" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="13,20" }
+
+
+; WARN: warning: <unknown>:0:0: failed to meet occupancy target given by 'amdgpu-waves-per-eu' in 'min_num_agpr_occ2_13_20': desired occupancy was 2, final occupancy is 1
+; WARN: warning: inline asm clobber list contains reserved registers: a16 at line 15
+; WARN: warning: inline asm clobber list contains reserved registers: a20 at line 15
+; WARN: warning: inline asm clobber list contains reserved registers: v240 at line 15
+define amdgpu_kernel void @min_num_agpr_occ2_13_20() #14 {
+ call void asm sideeffect "; clobber $0","~{a15}"(), !srcloc !{i32 15}
+ call void asm sideeffect "; clobber $0","~{a16}"(), !srcloc !{i32 15}
+ call void asm sideeffect "; clobber $0","~{a20}"(), !srcloc !{i32 15}
+
+ call void asm sideeffect "; clobber $0","~{v239}"(), !srcloc !{i32 15}
+ call void asm sideeffect "; clobber $0","~{v240}"(), !srcloc !{i32 15}
+
+ ret void
+}
+
+attributes #14 = { "amdgpu-waves-per-eu"="2,2" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="13,20" }
+
+
+; Test maximum exceeds the hardware limit.
+define amdgpu_kernel void @min_num_agpr_occ1_13_257() #15 {
+ call void asm sideeffect "; clobber $0","~{a255}"(), !srcloc !{i32 16}
+ call void asm sideeffect "; clobber $0","~{v255}"(), !srcloc !{i32 16}
+ ret void
+}
+
+attributes #15 = { "amdgpu-waves-per-eu"="1,1" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="13,257" }
+
+
+; Test min and max exceeds the hardware limit.
+define amdgpu_kernel void @min_num_agpr_occ1_257_257() #16 {
+ call void asm sideeffect "; clobber $0","~{a255}"(), !srcloc !{i32 17}
+ call void asm sideeffect "; clobber $0","~{v255}"(), !srcloc !{i32 17}
+ ret void
+}
+
+attributes #16 = { "amdgpu-waves-per-eu"="1,1" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="257,257" }
+
+
+; Test round up hits the hardware limit
+define amdgpu_kernel void @min_num_agpr_occ1_255_255() #17 {
+ call void asm sideeffect "; clobber $0","~{a255}"(), !srcloc !{i32 18}
+ call void asm sideeffect "; clobber $0","~{v255}"(), !srcloc !{i32 18}
+ ret void
+}
+
+attributes #17 = { "amdgpu-waves-per-eu"="1,1" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="255,255" }
+
+
+; Test round up hits the hardware limit
+define amdgpu_kernel void @min_num_agpr_occ1_253_259() #18 {
+ call void asm sideeffect "; clobber $0","~{a255}"(), !srcloc !{i32 19}
+ call void asm sideeffect "; clobber $0","~{v255}"(), !srcloc !{i32 19}
+ ret void
+}
+
+attributes #18 = { "amdgpu-waves-per-eu"="1,1" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="253,259" }
+
+; With a minimum of 0, we are not required to allocate any AGPRs
+; WARN: warning: <unknown>:0:0: failed to meet occupancy target given by 'amdgpu-waves-per-eu' in 'min_num_agpr_occ4_0_64': desired occupancy was 4, final occupancy is 2
+; WARN: warning: inline asm clobber list contains reserved registers: a0 at line 20
+; WARN: warning: inline asm clobber list contains reserved registers: a63 at line 20
+; WARN: warning: inline asm clobber list contains reserved registers: a64 at line 20
+; WARN: warning: inline asm clobber list contains reserved registers: v128 at line 20
+define amdgpu_kernel void @min_num_agpr_occ4_0_64() #19 {
+ call void asm sideeffect "; clobber $0","~{a0}"(), !srcloc !{i32 20}
+ call void asm sideeffect "; clobber $0","~{a63}"(), !srcloc !{i32 20}
+ call void asm sideeffect "; clobber $0","~{a64}"(), !srcloc !{i32 20}
+ call void asm sideeffect "; clobber $0","~{v63}"(), !srcloc !{i32 20}
+ call void asm sideeffect "; clobber $0","~{v64}"(), !srcloc !{i32 20}
+ call void asm sideeffect "; clobber $0","~{v127}"(), !srcloc !{i32 20}
+ call void asm sideeffect "; clobber $0","~{v128}"(), !srcloc !{i32 20}
+ ret void
+}
+
+attributes #19 = { "amdgpu-waves-per-eu"="4,4" "amdgpu-flat-work-group-size"="64,64" "amdgpu-num-agpr"="0,64" }
+
+
+; With a non-0 minimum, we must allocate at least 4 AGPRs. The rest of
+; the budget is for VGPRs.
+; WARN: warning: <unknown>:0:0: failed to meet occupancy target given by 'amdgpu-waves-per-eu' in 'min_num_agpr_occ4_1_64': desired occupancy was 4, final occupancy is 2
+; WARN: warning: inline asm clobber list contains reserved registers: a4 at line 21
+; WARN: warning: inline asm clobber list contains reserved registers: a63 at line 21
+; WARN: warning: inline asm clobber list contains reserved registers: a64 at line 21
+; WARN: warning: inline asm clobber list contains reserved registers: v124 at line 21
+define amdgpu_kernel void @min_num_agpr_occ4_1_64() #20 {
+ call void asm sideeffect "; clobber $0","~{a0}"(), !srcloc !{i32 21}
+ call void asm sideeffect "; clobber $0","~{a3}"(), !srcloc !{i32 21}
+ call ...
[truncated]
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I found these ranges are very confusing. If I require minimum 0 AGPRs, that means I can require 1, 2, 3, etc. AGPRs, because they are all larger than the minimum. Why does it mean no AGPR? |
The name is confusing, particularly since it's not the same behavior as amdgpu-num-vgpr and amdgpu-num-sgpr (which I would really like to delete). It probably should be changed. The minimum is supposed to be the minimum possible requirement. If the minimum is 0, you cannot allocate any AGPRs. |
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So it means the minimum requirement to work and if it is 0, it means I don't really need AGPRs to work? |
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This provides a range to decide how to subdivide the vector register budget on gfx90a+. A single value declares the minimum AGPRs that should be allocatable. Eventually this should replace amdgpu-no-agpr. I want this primarily for testing agpr allocation behavior. We should have a heuristic try to detect a reasonable number of AGPRs to keep allocatable.
We hit the allocation error, but we probably should treat it as UB and only emit a warning.
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…lvm#128034) This provides a range to decide how to subdivide the vector register budget on gfx90a+. A single value declares the minimum AGPRs that should be allocatable. Eventually this should replace amdgpu-no-agpr. I want this primarily for testing agpr allocation behavior. We should have a heuristic try to detect a reasonable number of AGPRs to keep allocatable.
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This provides a range to decide how to subdivide the vector register
budget on gfx90a+. A single value declares the minimum AGPRs that
should be allocatable. Eventually this should replace amdgpu-no-agpr.
I want this primarily for testing agpr allocation behavior. We should
have a heuristic try to detect a reasonable number of AGPRs to keep
allocatable.