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8354231: x86: Purge FPU support from (Macro)Assembler after 32-bit x86 removal #24558

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8354231: x86: Purge FPU support from (Macro)Assembler after 32-bit x86 removal #24558

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81aef47
Fix
shipilev Apr 9, 2025
a7c7bc9
Merge branch 'master' into JDK-8354231-x86-assemblers-fpu
shipilev Apr 11, 2025
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374 changes: 0 additions & 374 deletions src/hotspot/cpu/x86/assembler_x86.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -12918,380 +12918,6 @@ void Assembler::edecl(Register dst, Register src, bool no_flags) {
(void) evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
emit_int8(0x48 | src->encoding());
}

// 64bit doesn't use the x87

void Assembler::fabs() {
emit_int16((unsigned char)0xD9, (unsigned char)0xE1);
}

void Assembler::fadd(int i) {
emit_farith(0xD8, 0xC0, i);
}

void Assembler::fadd_d(Address src) {
InstructionMark im(this);
emit_int8((unsigned char)0xDC);
emit_operand32(rax, src, 0);
}

void Assembler::fadd_s(Address src) {
InstructionMark im(this);
emit_int8((unsigned char)0xD8);
emit_operand32(rax, src, 0);
}

void Assembler::fadda(int i) {
emit_farith(0xDC, 0xC0, i);
}

void Assembler::faddp(int i) {
emit_farith(0xDE, 0xC0, i);
}

void Assembler::fchs() {
emit_int16((unsigned char)0xD9, (unsigned char)0xE0);
}

void Assembler::fcom(int i) {
emit_farith(0xD8, 0xD0, i);
}

void Assembler::fcomp(int i) {
emit_farith(0xD8, 0xD8, i);
}

void Assembler::fcomp_d(Address src) {
InstructionMark im(this);
emit_int8((unsigned char)0xDC);
emit_operand32(rbx, src, 0);
}

void Assembler::fcomp_s(Address src) {
InstructionMark im(this);
emit_int8((unsigned char)0xD8);
emit_operand32(rbx, src, 0);
}

void Assembler::fcompp() {
emit_int16((unsigned char)0xDE, (unsigned char)0xD9);
}

void Assembler::fcos() {
emit_int16((unsigned char)0xD9, (unsigned char)0xFF);
}

void Assembler::fdecstp() {
emit_int16((unsigned char)0xD9, (unsigned char)0xF6);
}

void Assembler::fdiv(int i) {
emit_farith(0xD8, 0xF0, i);
}

void Assembler::fdiv_d(Address src) {
InstructionMark im(this);
emit_int8((unsigned char)0xDC);
emit_operand32(rsi, src, 0);
}

void Assembler::fdiv_s(Address src) {
InstructionMark im(this);
emit_int8((unsigned char)0xD8);
emit_operand32(rsi, src, 0);
}

void Assembler::fdiva(int i) {
emit_farith(0xDC, 0xF8, i);
}

// Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
// is erroneous for some of the floating-point instructions below.

void Assembler::fdivp(int i) {
emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
}

void Assembler::fdivr(int i) {
emit_farith(0xD8, 0xF8, i);
}

void Assembler::fdivr_d(Address src) {
InstructionMark im(this);
emit_int8((unsigned char)0xDC);
emit_operand32(rdi, src, 0);
}

void Assembler::fdivr_s(Address src) {
InstructionMark im(this);
emit_int8((unsigned char)0xD8);
emit_operand32(rdi, src, 0);
}

void Assembler::fdivra(int i) {
emit_farith(0xDC, 0xF0, i);
}

void Assembler::fdivrp(int i) {
emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
}

void Assembler::ffree(int i) {
emit_farith(0xDD, 0xC0, i);
}

void Assembler::fild_d(Address adr) {
InstructionMark im(this);
emit_int8((unsigned char)0xDF);
emit_operand32(rbp, adr, 0);
}

void Assembler::fild_s(Address adr) {
InstructionMark im(this);
emit_int8((unsigned char)0xDB);
emit_operand32(rax, adr, 0);
}

void Assembler::fincstp() {
emit_int16((unsigned char)0xD9, (unsigned char)0xF7);
}

void Assembler::finit() {
emit_int24((unsigned char)0x9B, (unsigned char)0xDB, (unsigned char)0xE3);
}

void Assembler::fist_s(Address adr) {
InstructionMark im(this);
emit_int8((unsigned char)0xDB);
emit_operand32(rdx, adr, 0);
}

void Assembler::fistp_d(Address adr) {
InstructionMark im(this);
emit_int8((unsigned char)0xDF);
emit_operand32(rdi, adr, 0);
}

void Assembler::fistp_s(Address adr) {
InstructionMark im(this);
emit_int8((unsigned char)0xDB);
emit_operand32(rbx, adr, 0);
}

void Assembler::fld1() {
emit_int16((unsigned char)0xD9, (unsigned char)0xE8);
}

void Assembler::fld_s(Address adr) {
InstructionMark im(this);
emit_int8((unsigned char)0xD9);
emit_operand32(rax, adr, 0);
}


void Assembler::fld_s(int index) {
emit_farith(0xD9, 0xC0, index);
}

void Assembler::fldcw(Address src) {
InstructionMark im(this);
emit_int8((unsigned char)0xD9);
emit_operand32(rbp, src, 0);
}

void Assembler::fldenv(Address src) {
InstructionMark im(this);
emit_int8((unsigned char)0xD9);
emit_operand32(rsp, src, 0);
}

void Assembler::fldlg2() {
emit_int16((unsigned char)0xD9, (unsigned char)0xEC);
}

void Assembler::fldln2() {
emit_int16((unsigned char)0xD9, (unsigned char)0xED);
}

void Assembler::fldz() {
emit_int16((unsigned char)0xD9, (unsigned char)0xEE);
}

void Assembler::flog() {
fldln2();
fxch();
fyl2x();
}

void Assembler::flog10() {
fldlg2();
fxch();
fyl2x();
}

void Assembler::fmul(int i) {
emit_farith(0xD8, 0xC8, i);
}

void Assembler::fmul_d(Address src) {
InstructionMark im(this);
emit_int8((unsigned char)0xDC);
emit_operand32(rcx, src, 0);
}

void Assembler::fmul_s(Address src) {
InstructionMark im(this);
emit_int8((unsigned char)0xD8);
emit_operand32(rcx, src, 0);
}

void Assembler::fmula(int i) {
emit_farith(0xDC, 0xC8, i);
}

void Assembler::fmulp(int i) {
emit_farith(0xDE, 0xC8, i);
}

void Assembler::fnsave(Address dst) {
InstructionMark im(this);
emit_int8((unsigned char)0xDD);
emit_operand32(rsi, dst, 0);
}

void Assembler::fnstcw(Address src) {
InstructionMark im(this);
emit_int16((unsigned char)0x9B, (unsigned char)0xD9);
emit_operand32(rdi, src, 0);
}

void Assembler::fprem1() {
emit_int16((unsigned char)0xD9, (unsigned char)0xF5);
}

void Assembler::frstor(Address src) {
InstructionMark im(this);
emit_int8((unsigned char)0xDD);
emit_operand32(rsp, src, 0);
}

void Assembler::fsin() {
emit_int16((unsigned char)0xD9, (unsigned char)0xFE);
}

void Assembler::fsqrt() {
emit_int16((unsigned char)0xD9, (unsigned char)0xFA);
}

void Assembler::fst_d(Address adr) {
InstructionMark im(this);
emit_int8((unsigned char)0xDD);
emit_operand32(rdx, adr, 0);
}

void Assembler::fst_s(Address adr) {
InstructionMark im(this);
emit_int8((unsigned char)0xD9);
emit_operand32(rdx, adr, 0);
}

void Assembler::fstp_s(Address adr) {
InstructionMark im(this);
emit_int8((unsigned char)0xD9);
emit_operand32(rbx, adr, 0);
}

void Assembler::fsub(int i) {
emit_farith(0xD8, 0xE0, i);
}

void Assembler::fsub_d(Address src) {
InstructionMark im(this);
emit_int8((unsigned char)0xDC);
emit_operand32(rsp, src, 0);
}

void Assembler::fsub_s(Address src) {
InstructionMark im(this);
emit_int8((unsigned char)0xD8);
emit_operand32(rsp, src, 0);
}

void Assembler::fsuba(int i) {
emit_farith(0xDC, 0xE8, i);
}

void Assembler::fsubp(int i) {
emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
}

void Assembler::fsubr(int i) {
emit_farith(0xD8, 0xE8, i);
}

void Assembler::fsubr_d(Address src) {
InstructionMark im(this);
emit_int8((unsigned char)0xDC);
emit_operand32(rbp, src, 0);
}

void Assembler::fsubr_s(Address src) {
InstructionMark im(this);
emit_int8((unsigned char)0xD8);
emit_operand32(rbp, src, 0);
}

void Assembler::fsubra(int i) {
emit_farith(0xDC, 0xE0, i);
}

void Assembler::fsubrp(int i) {
emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
}

void Assembler::ftan() {
emit_int32((unsigned char)0xD9, (unsigned char)0xF2, (unsigned char)0xDD, (unsigned char)0xD8);
}

void Assembler::ftst() {
emit_int16((unsigned char)0xD9, (unsigned char)0xE4);
}

void Assembler::fucomi(int i) {
// make sure the instruction is supported (introduced for P6, together with cmov)
guarantee(VM_Version::supports_cmov(), "illegal instruction");
emit_farith(0xDB, 0xE8, i);
}

void Assembler::fucomip(int i) {
// make sure the instruction is supported (introduced for P6, together with cmov)
guarantee(VM_Version::supports_cmov(), "illegal instruction");
emit_farith(0xDF, 0xE8, i);
}

void Assembler::fwait() {
emit_int8((unsigned char)0x9B);
}

void Assembler::fxch(int i) {
emit_farith(0xD9, 0xC8, i);
}

void Assembler::fyl2x() {
emit_int16((unsigned char)0xD9, (unsigned char)0xF1);
}

void Assembler::frndint() {
emit_int16((unsigned char)0xD9, (unsigned char)0xFC);
}

void Assembler::f2xm1() {
emit_int16((unsigned char)0xD9, (unsigned char)0xF0);
}

void Assembler::fldl2e() {
emit_int16((unsigned char)0xD9, (unsigned char)0xEA);
}
#endif // !_LP64

// SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
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