Searching for explainations to define a new instruction in the "struct riscv-opcode "

[arkhan91]

Hi,

I am trying to interpret the statements mentioned in "const struct riscv_opcode riscv_opcodes[]" in riscv-opc.h.
for example

const struct riscv_opcode riscv_opcodes[] =

{
/* name,      isa,   operands, match, mask, match_func, pinfo.  */
....
{"and",       "I",   "d,s,j",  MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS },
....
{"add",       "I",   "d,s,t",  MATCH_ADD, MASK_ADD, match_opcode, 0 }
....
} ````

Is there any document or source where i can find how to pass right statement specially operands.
I trying to append the custom instruction . 
 

[aswaterman]

Not really, as this is an internal interface. I suggest finding an instruction that has identical operand formats and copying it.

Adding new operand formats requires modifying several places in tc-riscv.c and riscv-dis.c. I wouldn't recommend it unless truly necessary.

[arkhan91]

Can you please elaborate meaning of general operands like "d,s,t" ,"d,s,j" etc,
thanks

[aswaterman]

I can’t document them all, but offhand I know that:

d = integer rd
s = integer rs1
t = integer rs2
j = 12-bit I-type immediate

[TommyMurphyTM1234]

This is a list of all issues logged that I can find that relate to adding new instructions to the toolchain:

• How to add support for a new instruction? #1095
• Adding custom instruction to vector compiler #1055
• Adding custom instruction to the elf tool-chain #837
• How to Add custom instructions to riscv-elf-toolchain #782
• Adding rvv intrinsic to already installed toolchain #1003
• How to add a custom non-standard instruction type format #795
• how can I modify functionality of an instruction? #660
• question about adding "mod" instruction #543
• Searching for explainations to define a new instruction in the "struct riscv-opcode " #341
• adding new opode extensions #115

At this stage in the evolution of RISC-V,the majority of instruction addition will be done under the auspices of the relevant groups working on standardising, prototyping, and implementing/enhancing RISC-V extensions and their corresponding instructions. As such, there should be less of a demand for others to do so.

However, where somebody still wants to implement a non stadard custom extension/instruction here are some useful resources:

• GCC internals documentation: https://gcc.gnu.org/onlinedocs/gccint/
• https://hsandid.github.io/posts/risc-v-custom-instruction/
• https://ossg.bcs.org/blog/2020/10/29/adding-an-instruction-to-the-gnu-assembler/
• https://embdev.net/topic/228773
• https://groups.google.com/u/0/a/groups.riscv.org/g/sw-dev/c/sL_OHXYj3LY/m/NOm5Fwa3BAAJ
• https://forums.sifive.com/t/adding-custom-instruction-to-riscv-toolchain/4044/2