How to add a custom non-standard instruction type format

[MauSilvestrini]

Good morning to everyone, I want to add a custom non-standard instruction that should have the following type format:

This field format is not new for the RISC-V ISA, it resembles the R4-type format that is used for the encoding of some instructions in the standard extension RV32F for single precision floating point calculation. In that specific case the rs3 source register field has been replaced with the destination register called RD1, in which I want to write something.

I already find out how to encode this new instruction extension, but I’d like to know, as far as possible, the procedure on how to add this new instruction type format to the current RISCV toolchain ISA, in particular which files I have to modify in order to write a piece of code that allows to write onto the RD1 field.

Many thanks for your help.

[jim-wilson]

Binutils doesn't use instruction formats, except for the .insn pseudo op. If you want .insn support for your new instruction you might need to change that if the existing r4 instruction format support doesn't work.

Otherwise, instruction formats are irrrelevant, and all that matters are the MASK/MATCH bit masks, and the 'd' 's' 't' etc letters to specify operands. But if your format is close enough to r4 then you probably don't need a new operand letter.

[Nelson1225]

FYI, I suppose all instructions can be derived from the existing instruction formats, although some of them might look weird.

[Nelson1225]

This should help, riscvarchive/riscv-binutils-gdb#184

[MauSilvestrini]

Binutils doesn't use instruction formats, except for the .insn pseudo op. If you want .insn support for your new instruction you might need to change that if the existing r4 instruction format support doesn't work.

Otherwise, instruction formats are irrrelevant, and all that matters are the MASK/MATCH bit masks, and the 'd' 's' 't' etc letters to specify operands. But if your format is close enough to r4 then you probably don't need a new operand letter.

Many thanks for your help Mr Wilson, with this I fixed the problem releted to the riscv-toolchain. Best Regards.

[TommyMurphyTM1234]

This is a list of all issues logged that I can find that relate to adding new instructions to the toolchain:

• How to add support for a new instruction? #1095
• Adding custom instruction to vector compiler #1055
• Adding custom instruction to the elf tool-chain #837
• How to Add custom instructions to riscv-elf-toolchain #782
• Adding rvv intrinsic to already installed toolchain #1003
• How to add a custom non-standard instruction type format #795
• how can I modify functionality of an instruction? #660
• question about adding "mod" instruction #543
• Searching for explainations to define a new instruction in the "struct riscv-opcode " #341
• adding new opode extensions #115

At this stage in the evolution of RISC-V,the majority of instruction addition will be done under the auspices of the relevant groups working on standardising, prototyping, and implementing/enhancing RISC-V extensions and their corresponding instructions. As such, there should be less of a demand for others to do so.

However, where somebody still wants to implement a non stadard custom extension/instruction here are some useful resources:

• GCC internals documentation: https://gcc.gnu.org/onlinedocs/gccint/
• https://hsandid.github.io/posts/risc-v-custom-instruction/
• https://ossg.bcs.org/blog/2020/10/29/adding-an-instruction-to-the-gnu-assembler/
• https://embdev.net/topic/228773
• https://groups.google.com/u/0/a/groups.riscv.org/g/sw-dev/c/sL_OHXYj3LY/m/NOm5Fwa3BAAJ
• https://forums.sifive.com/t/adding-custom-instruction-to-riscv-toolchain/4044/2