the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
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Updated
Jul 18, 2020 - JavaScript
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
computer architecture course final project
This project involves designing a single-core RISC-V CPU using Verilog. The design includes an Arithmetic Logic Unit (ALU) with flags, an assembly to machine code converter, a control unit, a microarchitecture and memory initialization to ensure proper functioning of the CPU.
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