LPC55xxx SPI fixes #26371
LPC55xxx SPI fixes #26371
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agansari
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jukkar,
MaureenHelm,
pfalcon and
tbursztyka
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dts/arm/nxp/nxp_lpc55S6x_common.dtsi
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| <&gpio1 26 0>; | ||
| /* The comment below will allow using GPIO CS, | ||
| rather than Flexcomm SS*/ | ||
| /* cs-gpios = <&gpio0 20 0>,<&gpio1 1 0>,<&gpio1 12 0>, |
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Are these GPIOs defined by the SoC for CS purposes?
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@galak Yes, these pins are mapped on SoC to be used as spi slave select. This means they are wired as CS for SPI devices on the evaluation boards.
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Comment about GPIO CS needs to be fixed after #26269 was merged, e.g. /* cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>, ....*/
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@jfischer-phytec-iot i've updated the dts file
@MaureenHelm cleaned up the commits |
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@MaureenHelm done! |
One more time please. :( |
Reverts part of 3722c64 commit. Reverts dummy buffer and uses NULL pointers. Signed-off-by: Andrei Gansari <[email protected]>
Flexcomm's SPI SSEL (or CS) will be held until frame end. FIFOWR[EOT] (kSPI_FrameAssert enum) is the register not set. Signed-off-by: Andrei Gansari <[email protected]>
Disables GPIO CS in order to use Flexcomm's SS as chip select issues were resolved. Signed-off-by: Andrei Gansari <[email protected]>
Okay, I dropped west.yaml commit as a newer commit is already upstream on master. |
Depends on: zephyrproject-rtos/hal_nxp#46