Add rt1180 spi/edma support

boards/nxp/mimxrt1180_evk/doc/index.rst

@@ -120,6 +120,10 @@ configuration supports the following hardware features:
 +-----------+------------+-------------------------------------+
 | I3C       | on-chip    | i3c                                 |
 +-----------+------------+-------------------------------------+
+| DMA       | on-chip    | dma                                 |
++-----------+------------+-------------------------------------+
+| SPI       | on-chip    | spi                                 |
++-----------+------------+-------------------------------------+
 
 The default configuration can be found in the defconfig file:
 :zephyr_file:`boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33_defconfig`
@@ -143,6 +147,14 @@ The MIMXRT1180 SoC has six pairs of pinmux/gpio controllers.
 +---------------+-----------------+---------------------------+
 | GPIO_AON_09   | LPUART1_RX      | UART Console              |
 +---------------+-----------------+---------------------------+
+| GPIO_SD_B1_00 | SPI1_CS0        | spi                       |
++---------------+---------------------------------------------+
+| GPIO_SD_B1_01 | SPI1_CLK        | spi                       |
++---------------+---------------------------------------------+
+| GPIO_SD_B1_02 | SPI1_SDO        | spi                       |
++---------------+---------------------------------------------+
+| GPIO_SD_B1_03 | SPI1_SDI        | spi                       |
++---------------+---------------------------------------------+
 
 System Clock
 ============

boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi

@@ -73,6 +73,29 @@
 		};
 	};
 
+	pinmux_lpuart3: pinmux_lpuart3 {
+		group0 {
+			pinmux = <&iomuxc_gpio_ad_14_lpuart3_rxd>,
+				<&iomuxc_gpio_ad_13_lpuart3_txd>;
+			drive-strength = "high";
+			slew-rate = "fast";
+		};
+	};
+
+	pinmux_lpuart3_sleep: pinmux_lpuart3_sleep {
+		group0 {
+			pinmux = <&iomuxc_gpio_ad_14_gpio4_io14>;
+			drive-strength = "high";
+			bias-pull-up;
+			slew-rate = "fast";
+		};
+		group1 {
+			pinmux = <&iomuxc_gpio_ad_13_lpuart3_txd>;
+			drive-strength = "high";
+			slew-rate = "fast";
+		};
+	};
+
 	/* Connected to FXLS8974 */
 	pinmux_lpi2c2: pinmux_lpi2c2 {
 		group0 {

boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi

@@ -47,6 +47,12 @@
 	pinctrl-names = "default", "sleep";
 };
 
+&lpuart3 {
+	pinctrl-0 = <&pinmux_lpuart3>;
+	pinctrl-1 = <&pinmux_lpuart3_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
 &user_button {
 	status = "okay";
 };
@@ -152,3 +158,10 @@
 
 p3t1755dp_ard_i3c_interface: &i3c2 {};
 p3t1755dp_ard_i2c_interface: &lpi2c2 {};
+
+&lpspi3 {
+	dmas = <&edma4 1 13>, <&edma4 2 12>;
+	dma-names = "rx", "tx";
+	pinctrl-0 = <&pinmux_lpspi3>;
+	pinctrl-names = "default";
+};

boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts

@@ -79,3 +79,15 @@
 &i3c2 {
 	status = "okay";
 };
+
+&lpspi3 {
+	status = "okay";
+};
+
+&edma3 {
+	status = "okay";
+};
+
+&edma4 {
+	status = "okay";
+};

boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml

@@ -25,4 +25,6 @@ supported:
   - pwm
   - uart
   - i3c
+  - dma
+  - spi
 vendor: nxp

boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts

@@ -51,3 +51,15 @@
 &i3c2 {
 	status = "okay";
 };
+
+&lpspi3 {
+	status = "okay";
+};
+
+&edma3 {
+	status = "okay";
+};
+
+&edma4 {
+	status = "okay";
+};

boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml

@@ -24,4 +24,6 @@ supported:
   - pwm
   - uart
   - i3c
+  - dma
+  - spi
 vendor: nxp

drivers/clock_control/clock_control_mcux_ccm_rev2.c

@@ -82,10 +82,16 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
 #endif
 
 #ifdef CONFIG_SPI_MCUX_LPSPI
+#if defined(CONFIG_SOC_SERIES_IMXRT118X)
+	case IMX_CCM_LPSPI0102_CLK:
+		clock_root = kCLOCK_Root_Lpspi0102 + instance;
+		break;
+#else
 	case IMX_CCM_LPSPI1_CLK:
 		clock_root = kCLOCK_Root_Lpspi1 + instance;
 		break;
-#endif
+#endif /* CONFIG_SOC_SERIES_IMXRT118X */
+#endif /* CONFIG_SPI_MCUX_LPSPI */
 
 #ifdef CONFIG_UART_MCUX_LPUART
 #if defined(CONFIG_SOC_SERIES_IMXRT118X)
@@ -117,6 +123,15 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
 		break;
 #endif
 
+#ifdef CONFIG_DMA_MCUX_EDMA_V4
+	case IMX_CCM_EDMA3_CLK:
+		clock_root = kCLOCK_Root_M33;
+		break;
+	case IMX_CCM_EDMA4_CLK:
+		clock_root = kCLOCK_Root_Wakeup_Axi;
+		break;
+#endif
+
 #ifdef CONFIG_PWM_MCUX
 #if defined(CONFIG_SOC_SERIES_IMXRT118X)
 	case IMX_CCM_PWM_CLK:

drivers/dma/dma_mcux_edma.c

@@ -277,6 +277,28 @@ static void dma_mcux_edma_error_irq_handler(const struct device *dev)
 }
 #endif
 
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(channels_shared_irq_mask)
+static void dma_mcux_edma_multi_channels_irq_handler(const struct device *dev, uint32_t idx,
+			uint32_t *buf, uint32_t mask_width)
+{
+	uint32_t *num = &buf[mask_width * idx];
+	uint32_t count = 0;
+
+	for (int _i = 0; _i < mask_width; _i++) {
+		uint32_t value = (*num);
+
+		while (value > 0) {
+			if ((value & 0x1) == 1) {
+				dma_mcux_edma_irq_handler(dev, count);
+			}
+			value = value >> 1;
+			count++;
+		}
+		num++;
+	}
+}
+#endif
+
 /* Configure a channel */
 static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel,
 				   struct dma_config *config)
@@ -861,10 +883,22 @@ static int dma_mcux_edma_init(const struct device *dev)
 			    irq_enable(DT_INST_IRQ_BY_IDX(n, idx, irq));	\
 	}
 
+#define EDMA_CHANNELS_MASK(n) static uint32_t edma_channel_mask_##n[] =  \
+				DT_PROP(DT_DRV_INST(n), channels_shared_irq_mask);
+
+#define GET_EDMA_CHANNEL_SHARED_IRQ_MASK_WIDTH(n) \
+			(DT_INST_PROP(n, dma_channels) / 32)
+
+#define EDMA_CHANNELS_SHARED_REGISTER_IN_IRQ(dev, idx, n) \
+		dma_mcux_edma_multi_channels_irq_handler(dev, idx, edma_channel_mask_##n, \
+			GET_EDMA_CHANNEL_SHARED_IRQ_MASK_WIDTH(n));
+
 #define DMA_MCUX_EDMA_IRQ_DEFINE(idx, n)					\
 	static void dma_mcux_edma_##n##_irq_##idx(const struct device *dev)	\
 	{									\
-		dma_mcux_edma_irq_handler(dev, idx);				\
+		COND_CODE_1(DT_INST_NODE_HAS_PROP(n, channels_shared_irq_mask), \
+			(EDMA_CHANNELS_SHARED_REGISTER_IN_IRQ(dev, idx, n)),	\
+			(dma_mcux_edma_irq_handler(dev, idx);))	\
 										\
 		IF_ENABLED(UTIL_BOOL(DT_INST_PROP(n, irq_shared_offset)),	\
 			  (dma_mcux_edma_irq_handler(dev,			\
@@ -877,6 +911,8 @@ static int dma_mcux_edma_init(const struct device *dev)
 	IRQ_CONFIG(n, idx, dma_mcux_edma_##n##_irq_##idx)
 
 #define DMA_MCUX_EDMA_CONFIG_FUNC(n)						\
+	IF_ENABLED(DT_INST_NODE_HAS_PROP(n, channels_shared_irq_mask), \
+				(EDMA_CHANNELS_MASK(n))) \
 	LISTIFY(NUM_IRQS_WITHOUT_ERROR_IRQ(n), DMA_MCUX_EDMA_IRQ_DEFINE, (), n) \
 	static void dma_imx_config_func_##n(const struct device *dev)		\
 	{									\