Add CAN driver support for Renesas RZ/G3S #83778

nhutnguyenkc · 2025-01-10T07:59:24Z

Add CAN driver support for Renesas RZ/G3S.

Since RZ/G3S does not support to calculate perfectly the sample point of 87,5%, so the test update is required.

zephyrbot · 2025-01-10T08:00:25Z

The following west manifest projects have changed revision in this Pull Request:

Name	Old Revision	New Revision	Diff

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henrikbrixandersen · 2025-01-10T11:23:06Z

tests/drivers/can/api/src/canfd.c

@@ -527,7 +527,11 @@ ZTEST_USER(canfd, test_set_timing_data_while_started)
 	struct can_timing timing = { 0 };
 	int err;

+#ifdef CONFIG_CAN_RENESAS_RZ_CANFD


No SoC/driver/board specific #ifdefs in generic API tests, please. You need to find another solution.

Understood. I have reverted the change. Unfortunately, RZ/G3S cannot calculate the sample point of 87.5% accurately, so the test_set_timing_data_while_started fail. Is it acceptable if we change the err check at line 531 to range check as below (in fact, 25 is enough for us)

zassert_between_inclusive(err, 0, 50, "failed to calculate data timing (err %d)", err);

@henrikbrixandersen , could you please confirm my above solution. Thanks

str4t0m

@nhutnguyenkc I am not very familiar with the renesas ecosystem, however this driver seems to use exactly the same fsp API as the existing renesas_ra driver.
In a quick glance at the hal the only difference in the header I can see are the not-/availabilty of canfd_txmb_merge_mode, e_canfd_tx_buffer, and common fifo.
And with the exception of some initialization stuff the code seems to match that driver nearly exactly.
Therefore I would suggest to keep the different compatibles, but factor out the common stuff of the two drivers.
Ideally the clock control driver would also be merged before this driver, then they would likely match even more.

str4t0m · 2025-02-09T18:35:55Z

boards/renesas/rzg3s_smarc/doc/index.rst

+| CANFD     | on-chip    | can                                 |
+-----------+------------+-------------------------------------+


This should be part of the board commit. Same for the change in the rzg3s_smarc_r9a08g045s33gbg_cm33.yaml

Thanks. I have moved them to board commit.

str4t0m · 2025-02-09T20:05:22Z

drivers/can/can_renesas_rz_canfd.c

+static int can_renesas_rz_get_core_clock(const struct device *dev, uint32_t *rate)
+{
+	const struct can_renesas_rz_cfg *cfg = dev->config;


Clock control driver not yet implemented, would make commonality between with the ra series even bigger.

Thanks. I have implemented clock control driver for can. It took a while to get clock control merged.

henrikbrixandersen

Did you consider the refactoring proposed in #83778 (review) ?

henrikbrixandersen · 2025-02-17T22:02:39Z

tests/drivers/can/api/src/canfd.c

@@ -528,7 +528,7 @@ ZTEST_USER(canfd, test_set_timing_data_while_started)
 	int err;

 	err = can_calc_timing_data(can_dev, &timing, TEST_BITRATE_3, TEST_SAMPLE_POINT);
-	zassert_ok(err, "failed to calculate data timing (err %d)", err);
+	zassert_between_inclusive(err, 0, 50, "failed to calculate data timing (err %d)", err);


This needs to be split out into it's own PR with proper description instead of being somewhat "hidden" in this larger PR.

Understood. I have reverted this change, and will update it in a separate PR.

henrikbrixandersen · 2025-02-17T22:03:19Z

tests/drivers/can/api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay

How come CAN is not enabled on the board level?

Thanks. I moved it to the board commit and dropped the test commit.

henrikbrixandersen · 2025-02-17T22:03:26Z

tests/drivers/can/timing/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay

How come CAN is not enabled on the board level?

Thanks. I moved it to the board commit and dropped the test commit.

nhutnguyenkc · 2025-02-18T04:06:09Z

I am not very familiar with the renesas ecosystem, however this driver seems to use exactly the same fsp API as the existing renesas_ra driver. In a quick glance at the hal the only difference in the header I can see are the not-/availabilty of canfd_txmb_merge_mode, e_canfd_tx_buffer, and common fifo. And with the exception of some initialization stuff the code seems to match that driver nearly exactly. Therefore I would suggest to keep the different compatibles, but factor out the common stuff of the two drivers. Ideally the clock control driver would also be merged before this driver, then they would likely match even more.

Thanks for your feedback. For the coexistence of CAN driver of renesas_rz and renesas_ra, let me explain a bit. They are two different product lines (RA is MCU, RZ is MPU) having two different FSP code base (hal_renesas). You may see small differences in case of RZ/G3S, but when other RZ devices come, the difference will be bigger, and the code would look too messy if it is shared between RZ and RA. In addition to the points that you have listed out (canfd_txmb_merge_mode, e_canfd_tx_buffer, and common fifo), clock, hardware configuration, direct register accesses are the points keeping them separate. These were also considered internally before concluding implementing a different code base.

nhutnguyenkc · 2025-03-12T07:42:30Z

I just rebased to resolve conflict

nhutnguyenkc · 2025-03-17T06:56:49Z

Rebase to resolve conflicts

nhutnguyenkc · 2025-03-21T06:07:41Z

Just rebase to resolve conflicts

nhutnguyenkc · 2025-03-28T06:51:04Z

Hi @thaoluonguw , @duynguyenxa , could you please help me review this PR to move it forward? Thanks

binhnguyen2434

LGTM!

thaoluonguw · 2025-04-09T04:50:47Z

boards/renesas/rzg3s_smarc/doc/index.rst

+| CANFD     | on-chip    | can                                 |
+-----------+------------+-------------------------------------+


@nhutnguyenkc : May I confirm that do you have plan to have a PR to update for document of current RZ boards?
If it is yes, I am okie with this temporary update. Thanks.

@thaoluonguw Yes, I do. Since there are some other PRs waiting for merging, so I don't want to rebase all of them. I will update it in a separate PR.

thaoluonguw · 2025-04-09T04:52:01Z

drivers/can/Kconfig.renesas_rz

@@ -0,0 +1,11 @@
+# Copyright (c) 2024 Renesas Electronics Corporation


@nhutnguyenkc : Please update for copyright year. Thanks.

Thanks. I updated copyright year

thaoluonguw · 2025-04-09T04:52:54Z

drivers/can/can_renesas_rz_canfd.c

@@ -0,0 +1,1048 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation


Please update for copyright year.

I updated copyright year

thaoluonguw · 2025-04-09T05:29:02Z

drivers/can/can_renesas_rz_canfd.c

+		LOG_DBG("CAN bus initialize failed");
+		return -EIO;
+	}
+
+	/* Put CAN controller into stopped state */
+	ret = cfg->fsp_api->modeTransition(data->fsp_ctrl, CAN_OPERATION_MODE_HALT,
+					   CAN_TEST_MODE_DISABLED);
+	if (ret != FSP_SUCCESS) {
+		cfg->fsp_api->close(data->fsp_ctrl);
+		LOG_DBG("CAN bus initialize failed");


The debug log information is same with previous failing. Can we improve for it?

I fixed it. Please help me check again.

thaoluonguw · 2025-04-09T05:51:22Z

dts/arm/renesas/rz/rzg/r9a08g045.dtsi

+	can_clk: can-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+		#clock-cells = <0>;
+	};


May I confirm the meaning of this adding? I think that this is external clock, and it doesn't belong to Soc layer.

In case of G3S, it is allowed to choose clock source from on-chip peripheral clock or external clock. Users can choose to use external clock by overriding this node's frequency at board level. Btw, I add a note External CAN clock - to be overridden by boards that provide it to this node

thaoluonguw · 2025-04-09T05:51:40Z

dts/bindings/can/renesas,rz-canfd-global.yaml

@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation


Please update the copyright year.

I updated copyright year

thaoluonguw · 2025-04-09T05:51:54Z

dts/bindings/can/renesas,rz-canfd.yaml

@@ -0,0 +1,26 @@
+# Copyright (c) 2024 Renesas Electronics Corporation


Same comment

I updated copyright year

Add CAN driver support for Renesas RZ/G3S Signed-off-by: Hieu Nguyen <[email protected]> Signed-off-by: Nhut Nguyen <[email protected]>

Add CAN nodes to Renesas RZ/G3S devicetree Signed-off-by: Hieu Nguyen <[email protected]> Signed-off-by: Nhut Nguyen <[email protected]>

Add CAN support for board RZ/G3S-SMARC Signed-off-by: Hieu Nguyen <[email protected]> Signed-off-by: Nhut Nguyen <[email protected]>

zephyrbot added area: CAN platforms: Renesas RZ labels Jan 10, 2025

zephyrbot requested review from alexanderwachter, henrikbrixandersen, martinjaeger, str4t0m and tgorochowik January 10, 2025 08:00

zephyrbot assigned henrikbrixandersen Jan 10, 2025

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binhnguyen2434 previously approved these changes Apr 1, 2025

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Hieu Nguyen added 3 commits April 14, 2025 17:14

drivers: can: Initial support for RZ/G3S

c56d582

Add CAN driver support for Renesas RZ/G3S Signed-off-by: Hieu Nguyen <[email protected]> Signed-off-by: Nhut Nguyen <[email protected]>

dts: renesas: Add CAN support for RZ/G3S

dbc5171

Add CAN nodes to Renesas RZ/G3S devicetree Signed-off-by: Hieu Nguyen <[email protected]> Signed-off-by: Nhut Nguyen <[email protected]>

boards: renesas: rzg3s_smarc: Add CAN support

86767de

Add CAN support for board RZ/G3S-SMARC Signed-off-by: Hieu Nguyen <[email protected]> Signed-off-by: Nhut Nguyen <[email protected]>

nhutnguyenkc force-pushed the rzg3s_support_can branch from 2c03909 to 86767de Compare April 14, 2025 10:15

binhnguyen2434 approved these changes Apr 22, 2025

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binhnguyen2434 requested a review from thaoluonguw April 22, 2025 09:40

		\| CANFD \| on-chip \| can \|
		+-----------+------------+-------------------------------------+

		@@ -0,0 +1,11 @@
		# Copyright (c) 2024 Renesas Electronics Corporation

		@@ -0,0 +1,1048 @@
		/*
		* Copyright (c) 2024 Renesas Electronics Corporation

		@@ -0,0 +1,12 @@
		# Copyright (c) 2024 Renesas Electronics Corporation

		@@ -0,0 +1,26 @@
		# Copyright (c) 2024 Renesas Electronics Corporation

Add CAN driver support for Renesas RZ/G3S #83778

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Add CAN driver support for Renesas RZ/G3S #83778

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