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Enhancements for spi_dw driver #87716

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Merged
merged 3 commits into from
Apr 25, 2025
Merged

Enhancements for spi_dw driver #87716

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72ef60a
drivers: spi: dw: fix dfs offset in HSSI controller
myguitar Aug 23, 2024
5d3fe55
drivers: spi: dw: fix txftlr in HSSI controller
myguitar Aug 23, 2024
1c8dbab
drivers: spi: dw: read ssi component version
myguitar Aug 23, 2024
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20 changes: 19 additions & 1 deletion drivers/spi/spi_dw.c
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Original file line number Diff line number Diff line change
Expand Up @@ -226,7 +226,7 @@ static int spi_dw_configure(const struct device *dev,
}

/* Word size */
if (info->max_xfer_size == 32) {
if (!IS_ENABLED(CONFIG_SPI_DW_HSSI) && (info->max_xfer_size == 32)) {
ctrlr0 |= DW_SPI_CTRLR0_DFS_32(SPI_WORD_SIZE_GET(config->operation));
} else {
ctrlr0 |= DW_SPI_CTRLR0_DFS_16(SPI_WORD_SIZE_GET(config->operation));
Expand Down Expand Up @@ -323,6 +323,18 @@ static void spi_dw_update_txftlr(const struct device *dev,
} else if (spi->ctx.tx_len < dw_spi_txftlr_dflt) {
reg_data = spi->ctx.tx_len - 1;
}
} else {
#if defined(CONFIG_SPI_DW_HSSI) && defined(CONFIG_SPI_EXTENDED_MODES)
/*
* TXFTLR field in the TXFTLR register is valid only for
* Controller mode operation
*/
if (!spi->ctx.tx_len) {
reg_data = 0U;
} else if (spi->ctx.tx_len < dw_spi_txftlr_dflt) {
reg_data = (spi->ctx.tx_len - 1) << DW_SPI_TXFTLR_TXFTLR_SHIFT;
}
#endif
}

LOG_DBG("TxFTLR: %u", reg_data);
Expand Down Expand Up @@ -554,6 +566,12 @@ int spi_dw_init(const struct device *dev)
write_imr(dev, DW_SPI_IMR_MASK);
clear_bit_ssienr(dev);

/* SSI component version */
spi->version = read_ssi_comp_version(dev);
LOG_DBG("Version: %c.%c%c%c", (spi->version >> 24) & 0xff,
(spi->version >> 16) & 0xff, (spi->version >> 8) & 0xff,
spi->version & 0xff);

LOG_DBG("Designware SPI driver initialized on device: %p", dev);

err = spi_context_cs_configure_all(&spi->ctx);
Expand Down
6 changes: 6 additions & 0 deletions drivers/spi/spi_dw.h
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Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,7 @@ struct spi_dw_config {
struct spi_dw_data {
DEVICE_MMIO_RAM;
struct spi_context ctx;
uint32_t version; /* ssi comp version */
uint8_t dfs; /* dfs in bytes: 1,2 or 4 */
uint8_t fifo_diff; /* cannot be bigger than FIFO depth */
};
Expand Down Expand Up @@ -194,6 +195,11 @@ static int reg_test_bit(uint8_t bit, mm_reg_t addr, uint32_t off)
#define DW_SPI_CTRLR0_SRL_BIT (13)
#endif

#if defined(CONFIG_SPI_DW_HSSI) && defined(CONFIG_SPI_EXTENDED_MODES)
/* TXFTLR setting. Only valid for Controller operation mode. */
#define DW_SPI_TXFTLR_TXFTLR_SHIFT (16)
#endif

#define DW_SPI_CTRLR0_SCPH BIT(DW_SPI_CTRLR0_SCPH_BIT)
#define DW_SPI_CTRLR0_SCPOL BIT(DW_SPI_CTRLR0_SCPOL_BIT)
#define DW_SPI_CTRLR0_SRL BIT(DW_SPI_CTRLR0_SRL_BIT)
Expand Down