Add cva6 boards to twister and rectify minor issues found when testing with twister #88511
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The device tree entry for cva6 is currently missing a device tree node for the mtime and mtimecmp registers in the core-local interrupt controllers. This causes the RISC-V machine timer driver not to be built, causing build failures as the system clock is missing. This commit rectifies this by adding the corresponding device tree entry. Signed-off-by: Eric Ackermann <[email protected]>
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In hardware, cva6 currently only provides global disable/enable functions for the Dcache and Icache. Disabling and re-enabling them also has the effect of flushing and invalidating the cache. Future cva6 SoCs will add support RISC-V's standardized cache management operations. This commit provides a default implementation for all methods currently part of the cache API. These implementations can be overwritten at board or SoC level, as they use weak linking. Signed-off-by: Eric Ackermann <[email protected]>
This commit adds the necessary configurations for building and testing cva6 boards (cv64a6_genesys_2, cv32a6_genesys_2) with twister. This has been validated against commit 8a9d7a832b7121dd6f9be61a380d1d89ebf2a5f3 of the cva6 hardware project. Signed-off-by: Eric Ackermann <[email protected]>
The original commit uses the incorrect value 42 for CONFIG_MAX_IRQ_PER_AGGREGATOR for the cva6 family of SoCs, which is the total number of IRQs in the system. This commit corrects this to 30, the number of IRQs for the PLIC. Signed-off-by: Eric Ackermann <[email protected]>
The nullpointer address (0x0) is mapped to the debug module in cva6, making it a valid address. Thus, in the coredump test, trigger an exception using k_panic() instead. Signed-off-by: Eric Ackermann <[email protected]>
In the default configuration, cv32a6 does not have an FPU and does not implement RISC-V's F and D extensions. Hence, the FPU flags should not be added. In the future, a second SoC for cv32a6 systems with FPU can be added. Signed-off-by: Eric Ackermann <[email protected]>
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This PR adds twister support for the current cva6 boards (cv64a6, cv32a6).
It also rectifies two issues found with cva6's configuration:
This configuration has been tested using
twister --device-testingon the hardware.