soc: add OpenHW Group CVA6 SoC #77732

WorldofJARcraft · 2024-08-29T09:29:18Z

Adds support for the CVA6 family of RISC-V CPUs.
CVA6 is commonly found as a soft core CPU on FPGA designs. Different configurations and instruction set extensions can be configured, and different SoCs targeting various FPGA boards are available.
This commit adds support for the 64-bit configuration of CVA6, as well as two slightly different SoCs (the main difference being the Ethernet subsystem).
The configuration can also optionally target the hardware simulation environment (test harness) of the CVA6 project and can indicate test/failure to the environment.

WorldofJARcraft · 2024-09-02T12:54:37Z

Full support for this SoC depends on drivers for the Ethernet subsystem: #73986, #73982, #73926

nordicjm · 2024-11-06T11:53:18Z

boards/openhwgroup/cv32a6_arty_a7_100/Kconfig.cv32a6_arty_a7_100

@@ -0,0 +1,5 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+config BOARD_CV32A6_ARTY_A7_100


split this into commits, not going to review 77 files spanning multiple boards, multiple socs and even samples in a single commits

I have removed the boards and samples from this PR and created new PRs:

boards: openhwgroup: add CV64A6 on GenesysII board #81019

boards: openhwgroup: add CVA6 on GenesysII board #81015

boards: openhwgroup: add CVA6 on Arty A7 board #81018

boards: openhwgroup: add CVA6 Testbench #81017
I have kept the 32-bit and the 64-bit variants of the same board in the same PR, as they are otherwise identical.

Have this PR have a soc (in one commit), drivers (each in different commits) and one board (in another commit), then once that is merged you can add additional boards in a new PR each with their own commit

The Ethernet subsystem is not specific to this hardware (e.g., it is also used on ARM boards), so I will leave it as separate PRs.
This PR now has one commit with the SoC and one with a board in 32 and 64 bit variants.

kartben · 2024-11-06T12:00:44Z

@WorldofJARcraft please don't forget that new boards must come with associated documentation. See https://docs.zephyrproject.org/latest/hardware/porting/board_porting.html#contributing-your-board

WorldofJARcraft · 2024-11-06T12:04:30Z

@WorldofJARcraft please don't forget that new boards must come with associated documentation. See https://docs.zephyrproject.org/latest/hardware/porting/board_porting.html#contributing-your-board

Thank you for the reminder, I will finalize my changes and add the documentation before un-drafting the PR.

nordicjm

apply comments throughout, they have only been added to the first instance

nordicjm · 2024-11-07T10:30:08Z

dts/riscv/openhwgroup/cv32a6.dtsi

@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: Apache-2.0


/* comment style

nordicjm · 2024-11-07T10:30:22Z

dts/riscv/openhwgroup/cv32a6.dtsi

+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv32ima";
+


Suggested change

nordicjm · 2024-11-07T10:30:38Z

dts/riscv/openhwgroup/cv32a6.dtsi

+			};
+		};
+	};
+


Suggested change

dts/riscv/openhwgroup/cva6.dtsi

nordicjm · 2024-11-07T10:31:06Z

dts/riscv/openhwgroup/cva6.dtsi

+	ranges;
+
+	memory0:memory@80000000 {
+	    device_type = "memory";


tab indents

nordicjm · 2024-11-07T10:34:55Z

soc/openhwgroup/cva6/cv32a6/Kconfig.soc

+	default "cv32a6" if SOC_SERIES_CV32A6
+
+config SOC
+	default "cv32a6" if SOC_CV32A6


do you really need a soc series and a soc if they are the same value? If not, remove the soc series from Kconfig and soc.yml and just have the soc

There are several slightly different versions of the CVA6 32-bit SOC: with and without MMU, with and without FPU, and a RV32E version is currently being developed. I have added the least common denominator here, future PRs can add the other variants as soon as they are finalized.

All of the RV32I SoCs work with the config I provided, but the RV32E really needs to be separate (it has fewer registers).

Are they going to be under the CV32A6 soc series or something else? Because if it's going to be just a 1:1 mapping of SoC to SoC series, the series can go, it's not required

At least the embedded version will be - it has a near-identical configuration, but with the RV32E instead of the RV32I instruction set. There is also an ASIC version of the 32-bit SoC (the CV32A65X by Thales), which has some additional instruction set extensions enabled.

nordicjm · 2024-11-07T10:36:23Z

soc/openhwgroup/cva6/cv64a6/Kconfig

+# SPDX-License-Identifier: Apache-2.0
+# RISCV64 OpenHW Group cva6 configuration options
+
+config SOC_CV64A6_IMAFDC


have a config SOC_CV64A6 symbol which selects common this, then you can select the unique ones in the separate Kconfigs. And select the common Kconfig from Kconfig.soc

nordicjm · 2024-11-07T10:36:43Z

soc/openhwgroup/cva6/cv64a6/Kconfig.soc

+	default "cv64a6" if SOC_CV64A6_IMAFDC
+	default "cv64a6" if SOC_CV64A6_IMAC


Suggested change

default "cv64a6" if SOC_CV64A6_IMAFDC

default "cv64a6" if SOC_CV64A6_IMAC

default "cv64a6" if SOC_CV64A6

nordicjm · 2024-11-07T10:36:53Z

soc/openhwgroup/cva6/cva6.h

+
+#include <stdint.h>
+
+void z_cva6_finish_test(const int32_t status);


what is this?

One of the "board" configurations from the other PRs describes a verification harness in which the CVA6 CPU is run in verilator (a HDL simulator). This is used to run test programs in the simulator and check whether the CPU behaves as expected. To this end, the simulator provides an interface that allows completing the test case successfully or with an error code. This is exposed via this SoC-specific function.
The samples I added in #81017 show how this can be used in software.

I have added a comment that explains what the function does.

Should I remove this functionality from this PR and re-introduce it with the board that actually uses this?

From a brief look at this, it does seem to me that this more likely belongs with the board.

Only exception I can see is if any board using the cva6 SoC in one way or another can run with the verilator, which again means that all boards needs this function.
The next question though is, is a cva6.h file best place for simulator related functions ?

Would be nice if @WorldofJARcraft can give a more thoughouh explanation of the feature and any considerations of where this function could have been declared instead, and why this was not chosen.

I'm not seeing any response from @WorldofJARcraft here

I have removed this feature from the current PR.
I will re-introduce it in a separate commit when I add the board (actually a simulation environment, no physical board) that actually uses this.
In case the board is rejected, the feature is not really useful.
Please note that I also removed the poweroff functionality, as this is also only supported in the simulation environment currently.

nordicjm · 2024-11-07T10:37:55Z

dts/riscv/openhwgroup/cv32a6.dtsi

+
+#include "cva6.dtsi"
+
+// minimal configuration of CVA6 32-bit CPUs: no instruction set extensions,


Capitalise first letter of comments i.e. English

WorldofJARcraft · 2024-11-07T15:16:04Z

I have incorporated the requested changes and re-written the commits.

kartben

+1 for docs (I pushed a few fixes that were easier to directly tackle rather than commenting, hope you don't mind https://github.com/zephyrproject-rtos/zephyr/compare/4a509080a693f8cd385fbe2d06427239a03fb13d..ea5e092f390bebe62b3a5e97082bebf35174d9c2)

WorldofJARcraft · 2025-03-27T17:43:49Z

No problem, thanks for your help!

kartben · 2025-03-27T17:47:02Z

No problem, thanks for your help!

@WorldofJARcraft not sure anyone cares but if you do (which is fine of course!), maybe re-sign the commit?

WorldofJARcraft · 2025-03-27T17:56:31Z

I added my signature to the commit and made no changes otherwise.

soc/openhwgroup/cva6/Kconfig.defconfig

kartben

The comment I left is really only if this goes through another round of updates. Great work!

kartben · 2025-04-06T06:59:05Z

boards/openhwgroup/cv32a6_genesys_2/doc/index.rst

+References
+**********
+
+.. _CVA6 documentation:


Suggested change

.. _CVA6 documentation:

.. target-notes::

.. _CVA6 documentation:

kartben

couple more documentation things probably worth fixing imo

kartben · 2025-04-09T16:22:56Z

dts/bindings/cpu/openhwgroup,cva6.yaml

+# Copyright (c) 2025 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: Specific device tree attributes for OpenHWGroup cva6 CPUs


Suggested change

description: Specific device tree attributes for OpenHWGroup cva6 CPUs

description: OpenHW Group CVA6 CPU

kartben · 2025-04-09T16:24:12Z

@nordicjm please revisit

nordicjm · 2025-04-10T06:25:59Z

Awaiting response from @WorldofJARcraft on #77732 (comment)

WorldofJARcraft · 2025-04-10T07:04:16Z

Awaiting response from @WorldofJARcraft on #77732 (comment)

Sorry, I forgot about this thread @nordicjm.

Adds support for the CVA6 family of RISC-V CPUs. CVA6 is commonly found as a soft core CPU on FPGA designs. Different configurations and instruction set extensions can be configured, and different SoCs targeting various FPGA boards are available. This commit adds support for the 32-bit and 64-bit configurations of CVA6, as well as three slightly different SoCs (a minimal 32-bit configuration, a 64-bit configuration without FPU, a 64-bit configuration with FPU). Signed-off-by: Eric Ackermann <[email protected]>

Adds support for the CVA6 CPU on a Genesys 2 FPGA board (https://github.com/openhwgroup/cva6). The SoC currently contains the CVA6 CPU with the SV39 MMU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, and I2C controller for on-board audio, a GPIO and the lowRISC ethernet subsystem. Two slightly different versions of the board are added, with a 64-bit and a 64-bit configuration of CVA6, respectively. Signed-off-by: Eric Ackermann <[email protected]>

kartben · 2025-04-11T13:46:47Z

boards/openhwgroup/cv64a6_genesys_2/doc/index.rst

+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: cv64a6_genesys_2
+   :goals: build flash


@WorldofJARcraft have you actually tested this? It doesn't seem like it's possible to build a hello world at the moment?
Also, you will want to add twister files so that this board is tested in CI, this will allow to catch such issues in the future. Somehow this was missed during the review of this PR.

I tried to kick things off here but you're probably better positioned to take it it from here :)

@kartben I have tested the configuration, but against an outdated main branch, sorry.
Apparently, at some point during when I initially composed the PR and now, the device tree requirements for the RISC-V machine timer changed.
I have force-pushed a corrected version to the branch I have been using for this PR. I am also making the necessary changes for integrating the board into twister.
Should I make a new PR with the necessary changes or can I somehow overwrite the commits that have already been merged?

@WorldofJARcraft Thanks for the quick feedback, really appreciated! It needs to be a new branch/PR based off of current main. FWIW what you now have in your branch looks in a much better shape but I encourage you to actually run Twister to check where things are at (for example I don't think you want "simulation: qemu" in there)

west twister -p cv32a6_genesys_2

@kartben I have made a new PR for this: #88511
I have successfully tested the new PR in hardware against cv64a6.
I will set up and test on cv32a6 next week.
Until then, I will leave the PR in draft mode.

Very nice, thanks for the update!

WorldofJARcraft marked this pull request as draft August 29, 2024 09:29

WorldofJARcraft force-pushed the openhwgroup-cv64a6-soc branch 3 times, most recently from f442e4e to eda4bed Compare August 29, 2024 13:35

WorldofJARcraft mentioned this pull request Aug 29, 2024

boards: openhwgroup: add CV64A6 on GenesysII board #77734

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WorldofJARcraft mentioned this pull request Oct 8, 2024

drivers: dma: Add Xilinx AXI DMA driver #73926

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WorldofJARcraft force-pushed the openhwgroup-cv64a6-soc branch 2 times, most recently from 6ac17ac to 7f79bdf Compare November 6, 2024 11:42

This was referenced Nov 6, 2024

boards: openhwgroup: add CV64A6 Testbench #77789

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boards: openhwgroup: add CV64A6 on GenesysII board #77792

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Blueballs #80772

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WorldofJARcraft dismissed kartben’s stale review via a83ee5e March 28, 2025 09:31

WorldofJARcraft force-pushed the openhwgroup-cv64a6-soc branch 3 times, most recently from ec1fa35 to 5b9d4bd Compare March 28, 2025 09:35

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WorldofJARcraft added 2 commits April 10, 2025 09:05

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kartben merged commit c2f024e into zephyrproject-rtos:main Apr 11, 2025
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		default "cv64a6" if SOC_CV64A6_IMAFDC
		default "cv64a6" if SOC_CV64A6_IMAC

	default "cv64a6" if SOC_CV64A6_IMAFDC
	default "cv64a6" if SOC_CV64A6_IMAC
	default "cv64a6" if SOC_CV64A6


		#include <stdint.h>

		void z_cva6_finish_test(const int32_t status);


		#include "cva6.dtsi"

		// minimal configuration of CVA6 32-bit CPUs: no instruction set extensions,

	description: Specific device tree attributes for OpenHWGroup cva6 CPUs
	description: OpenHW Group CVA6 CPU

soc: add OpenHW Group CVA6 SoC #77732

soc: add OpenHW Group CVA6 SoC #77732

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WorldofJARcraft commented Aug 29, 2024

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