Initial support for ARM Cortex-R

CODEOWNERS

@@ -18,6 +18,7 @@
 /arch/arm/                                @MaureenHelm @galak @ioannisg
 /arch/arm/core/cortex_m/cmse/             @ioannisg
 /arch/arm/include/cortex_m/cmse.h         @ioannisg
+/arch/arm/core/cortex_r/                  @MaureenHelm @galak @ioannisg @bbolen
 /arch/common/                             @andrewboie @ioannisg @andyross
 /arch/x86_64/                             @andyross
 /soc/arc/snps_*/                          @vonhust @ruuddw
@@ -153,6 +154,8 @@
 /drivers/serial/uart_liteuart.c           @mateusz-holenko @kgugala @pgielda
 /drivers/serial/Kconfig.rtt               @carlescufi @pkral78
 /drivers/serial/uart_rtt.c                @carlescufi @pkral78
+/drivers/serial/Kconfig.xlnx              @wjliang
+/drivers/serial/uart_xlnx_ps.c            @wjliang
 /drivers/net/                             @jukkar @tbursztyka
 /drivers/ptp_clock/                       @jukkar
 /drivers/spi/                             @tbursztyka
@@ -162,6 +165,7 @@
 /drivers/timer/altera_avalon_timer_hal.c  @wentongwu
 /drivers/timer/riscv_machine_timer.c      @nategraff-sifive @kgugala @pgielda
 /drivers/timer/litex_timer.c              @mateusz-holenko @kgugala @pgielda
+/drivers/timer/xlnx_psttc_timer.c         @wjliang
 /drivers/usb/                             @jfischer-phytec-iot @finikorg
 /drivers/usb/device/usb_dc_stm32.c        @ydamigos @loicpoulain
 /drivers/i2c/i2c_ll_stm32*                @ldts @ydamigos
@@ -183,6 +187,8 @@
 /dts/riscv/rv32m1*                        @MaureenHelm
 /dts/riscv/riscv32-fe310.dtsi             @nategraff-sifive
 /dts/riscv/riscv32-litex-vexriscv.dtsi    @mateusz-holenko @kgugala @pgielda
+/dts/arm/armv7-r.dtsi                     @bbolen
+/dts/arm/xilinx/                          @bbolen
 /dts/xtensa/xtensa.dtsi                   @ydamigos
 /dts/bindings/                            @galak
 /dts/bindings/can/                        @alexanderwachter

arch/arm/CMakeLists.txt

@@ -7,6 +7,7 @@ set(ARCH_FOR_cortex-m4        armv7e-m        )
 set(ARCH_FOR_cortex-m23       armv8-m.base    )
 set(ARCH_FOR_cortex-m33       armv8-m.main+dsp)
 set(ARCH_FOR_cortex-m33+nodsp armv8-m.main    )
+set(ARCH_FOR_cortex-r4        armv7-r         )
 
 if(ARCH_FOR_${GCC_M_CPU})
     set(ARCH_FLAG -march=${ARCH_FOR_${GCC_M_CPU}})

arch/arm/core/CMakeLists.txt

@@ -33,3 +33,5 @@ add_subdirectory_ifdef(CONFIG_ARM_MPU cortex_m/mpu)
 add_subdirectory_ifdef(CONFIG_CPU_CORTEX_M_HAS_CMSE cortex_m/cmse)
 add_subdirectory_ifdef(CONFIG_ARM_SECURE_FIRMWARE cortex_m/tz)
 add_subdirectory_ifdef(CONFIG_ARM_NONSECURE_FIRMWARE cortex_m/tz)
+
+add_subdirectory_ifdef(CONFIG_CPU_CORTEX_R cortex_r)

arch/arm/core/Kconfig

@@ -29,6 +29,96 @@ config CPU_CORTEX_M
 	help
 	  This option signifies the use of a CPU of the Cortex-M family.
 
+config CPU_CORTEX_R
+	bool
+	select CPU_CORTEX
+	select HAS_FLASH_LOAD_OFFSET
+	help
+	  This option signifies the use of a CPU of the Cortex-R family.
+
+config ISA_THUMB2
+	bool
+	help
+	  From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
+
+	  Thumb-2 technology is the instruction set underlying the ARM Cortex
+	  architecture which provides enhanced levels of performance, energy
+	  efficiency, and code density for a wide range of embedded
+	  applications.
+
+	  Thumb-2 technology builds on the success of Thumb, the innovative
+	  high code density instruction set for ARM microprocessor cores, to
+	  increase the power of the ARM microprocessor core available to
+	  developers of low cost, high performance systems.
+
+	  The technology is backwards compatible with existing ARM and Thumb
+	  solutions, while significantly extending the features available to
+	  the Thumb instructions set. This allows more of the application to
+	  benefit from the best in class code density of Thumb.
+
+	  For performance optimized code Thumb-2 technology uses 31 percent
+	  less memory to reduce system cost, while providing up to 38 percent
+	  higher performance than existing high density code, which can be used
+	  to prolong battery-life or to enrich the product feature set. Thumb-2
+	  technology is featured in the  processor, and in all ARMv7
+	  architecture-based processors.
+
+config ISA_ARM
+	bool
+	help
+	  From: https://developer.arm.com/products/architecture/instruction-sets/a32-and-t32-instruction-sets
+
+	  A32 instructions, known as Arm instructions in pre-Armv8 architectures,
+	  are 32 bits wide, and are aligned on 4-byte boundaries. A32 instructions
+	  are supported by both A-profile and R-profile architectures.
+
+	  A32 was traditionally used in applications requiring the highest
+	  performance, or for handling hardware exceptions such as interrupts and
+	  processor start-up. Much of its functionality was subsumed into T32 with
+	  the introduction of Thumb-2 technology.
+
+config DATA_ENDIANNESS_LITTLE
+	bool
+	default y if CPU_CORTEX
+	help
+	  This is driven by the processor implementation, since it is fixed in
+	  hardware. The board should set this value to 'n' if the data is
+	  implemented as big endian.
+
+config STACK_ALIGN_DOUBLE_WORD
+	bool "Align stacks on double-words (8 octets)"
+	default y
+	help
+	  This is needed to conform to AAPCS, the procedure call standard for
+	  the ARM. It wastes stack space. The option also enforces alignment
+	  of stack upon exception entry on Cortex-M3 and Cortex-M4 (ARMv7-M).
+	  Note that for ARMv6-M, ARMv8-M, and Cortex-M7 MCUs stack alignment
+	  on exception entry is enabled by default and it is not configurable.
+
+config RUNTIME_NMI
+	bool "Attach an NMI handler at runtime"
+	select REBOOT
+	help
+	  The kernel provides a simple NMI handler that simply hangs in a tight
+	  loop if triggered. This fills the requirement that there must be an
+	  NMI handler installed when the CPU boots. If a custom handler is
+	  needed, enable this option and attach it via _NmiHandlerSet().
+
+config FAULT_DUMP
+	int "Fault dump level"
+	default 2
+	range 0 2
+	help
+	  Different levels for display information when a fault occurs.
+
+	  2: The default. Display specific and verbose information. Consumes
+		the most memory (long strings).
+
+	  1: Display general and short information. Consumes less memory
+		(short strings).
+
+	  0: Off.
+
 config BUILTIN_STACK_GUARD
 	bool "Thread Stack Guards based on built-in ARM stack limit checking"
 	depends on CPU_CORTEX_M_HAS_SPLIM
@@ -185,6 +275,7 @@ endchoice
 endmenu
 
 source "arch/arm/core/cortex_m/Kconfig"
+source "arch/arm/core/cortex_r/Kconfig"
 
 source "arch/arm/core/cortex_m/mpu/Kconfig"
 

arch/arm/core/cortex_m/Kconfig

@@ -75,34 +75,6 @@ config CPU_CORTEX_M7
 
 if CPU_CORTEX_M
 
-config ISA_THUMB2
-	bool
-	# Omit prompt to signify "hidden" option
-	help
-	  From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
-
-	  Thumb-2 technology is the instruction set underlying the ARM Cortex
-	  architecture which provides enhanced levels of performance, energy
-	  efficiency, and code density for a wide range of embedded
-	  applications.
-
-	  Thumb-2 technology builds on the success of Thumb, the innovative
-	  high code density instruction set for ARM microprocessor cores, to
-	  increase the power of the ARM microprocessor core available to
-	  developers of low cost, high performance systems.
-
-	  The technology is backwards compatible with existing ARM and Thumb
-	  solutions, while significantly extending the features available to
-	  the Thumb instructions set. This allows more of the application to
-	  benefit from the best in class code density of Thumb.
-
-	  For performance optimized code Thumb-2 technology uses 31 percent
-	  less memory to reduce system cost, while providing up to 38 percent
-	  higher performance than existing high density code, which can be used
-	  to prolong battery-life or to enrich the product feature set. Thumb-2
-	  technology is featured in the  processor, and in all ARMv7
-	  architecture-based processors.
-
 config CPU_CORTEX_M_HAS_SYSTICK
 	bool
 	# Omit prompt to signify "hidden" option
@@ -275,48 +247,6 @@ config LDREX_STREX_AVAILABLE
 	bool
 	default y
 
-config DATA_ENDIANNESS_LITTLE
-	bool
-	default y
-	help
-	  This is driven by the processor implementation, since it is fixed in
-	  hardware. The board should set this value to 'n' if the data is
-	  implemented as big endian.
-
-config STACK_ALIGN_DOUBLE_WORD
-	bool "Align stacks on double-words (8 octets)"
-	default y
-	help
-	  This is needed to conform to AAPCS, the procedure call standard for
-	  the ARM. It wastes stack space. The option also enforces alignment
-	  of stack upon exception entry on Cortex-M3 and Cortex-M4 (ARMv7-M).
-	  Note that for ARMv6-M, ARMv8-M, and Cortex-M7 MCUs stack alignment
-	  on exception entry is enabled by default and it is not configurable.
-
-config RUNTIME_NMI
-	bool "Attach an NMI handler at runtime"
-	select REBOOT
-	help
-	  The kernel provides a simple NMI handler that simply hangs in a tight
-	  loop if triggered. This fills the requirement that there must be an
-	  NMI handler installed when the CPU boots. If a custom handler is
-	  needed, enable this option and attach it via _NmiHandlerSet().
-
-config FAULT_DUMP
-	int "Fault dump level"
-	default 2
-	range 0 2
-	help
-	  Different levels for display information when a fault occurs.
-
-	  2: The default. Display specific and verbose information. Consumes
-		the most memory (long strings).
-
-	  1: Display general and short information. Consumes less memory
-		(short strings).
-
-	  0: Off.
-
 config XIP
 	default y
 

arch/arm/core/cortex_r/CMakeLists.txt

@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(
+  vector_table.S
+  reset.S
+  fault.c
+  reboot.c
+  stacks.c
+  )

arch/arm/core/cortex_r/Kconfig

@@ -0,0 +1,98 @@
+# Kconfig - ARM Cortex-R platform configuration options
+
+#
+# Copyright (c) 2018 Marvell
+# Copyright (c) 2018 Lexmark International, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+# NOTE: We have the specific core implementations first and outside of the
+# if CPU_CORTEX_R block so that SoCs can select which core they are using
+# without having to select all the options related to that core.  Everything
+# else is captured inside the if CPU_CORTEX_R block so they are not exposed
+# if one selects a different ARM Cortex Family (Cortex-A or Cortex-M)
+
+
+config CPU_CORTEX_R4
+	bool
+	select CPU_CORTEX_R
+	select ARMV7_R
+	select ARMV7_R_FP if CPU_HAS_FPU
+	help
+	  This option signifies the use of a Cortex-R4 CPU
+
+config CPU_CORTEX_R5
+	bool
+	select CPU_CORTEX_R
+	select ARMV7_R
+	select ARMV7_R_FP if CPU_HAS_FPU
+	help
+	  This option signifies the use of a Cortex-R5 CPU
+
+if CPU_CORTEX_R
+
+config ARMV7_R
+	bool
+	select ATOMIC_OPERATIONS_BUILTIN
+	select ISA_ARM
+	help
+	  This option signifies the use of an ARMv7-R processor
+	  implementation.
+
+	  From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
+	  The Armv7-R architecture implements a traditional Arm architecture with
+	  multiple modes and supports a Protected Memory System Architecture
+	  (PMSA) based on a Memory Protection Unit (MPU). It supports the Arm (32)
+	  and Thumb (T32) instruction sets.
+
+config ARMV7_R_FP
+	bool
+	depends on ARMV7_R
+	help
+	  This option signifies the use of an ARMv7-R processor
+	  implementation supporting the Floating-Point Extension.
+
+config ARMV7_EXCEPTION_STACK_SIZE
+	int "Undefined Instruction and Abort stack size (in bytes)"
+	default 256
+	help
+	  This option specifies the size of the stack used by the undefined
+	  instruction and data abort exception handlers.
+
+config ARMV7_FIQ_STACK_SIZE
+	int "FIQ stack size (in bytes)"
+	default 256
+	help
+	  This option specifies the size of the stack used by the FIQ handler.
+
+config ARMV7_SVC_STACK_SIZE
+	int "SVC stack size (in bytes)"
+	default 512
+	help
+	  This option specifies the size of the stack used by the SVC handler.
+
+config ARMV7_SYS_STACK_SIZE
+	int "SYS stack size (in bytes)"
+	default 1024
+	help
+	  This option specifies the size of the stack used by the system mode.
+
+menu "ARM Cortex-R options"
+	depends on CPU_CORTEX_R
+
+config RUNTIME_NMI
+	default y
+
+config LDREX_STREX_AVAILABLE
+	default y
+
+config GEN_ISR_TABLES
+	default y
+
+config GEN_IRQ_VECTOR_TABLE
+	default n
+
+endmenu
+
+endif # CPU_CORTEX_R

arch/arm/core/cortex_r/fault.c

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018 Lexmark International, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <kernel.h>
+#include <kernel_structs.h>
+
+/**
+ *
+ * @brief Fault handler
+ *
+ * This routine is called when fatal error conditions are detected by hardware
+ * and is responsible only for reporting the error. Once reported, it then
+ * invokes the user provided routine _SysFatalErrorHandler() which is
+ * responsible for implementing the error handling policy.
+ *
+ * This is a stub for more exception handling code to be added later.
+ */
+void _Fault(z_arch_esf_t *esf, u32_t exc_return)
+{
+	z_arm_fatal_error(K_ERR_CPU_EXCEPTION, esf);
+}
+
+void z_FaultInit(void)
+{
+}