Initial support for ARM Cortex-R #9316

bbolen · 2018-08-06T20:47:38Z

There have been a couple of requests for the addition of ARM Cortex-R support, e.g. #6545 and #5540.

I have started work for Cortex-R4 support for a project my company is doing. This PR represents work that gets the "shell" sample working on an R4. Basic context switching and interrupts using an R4 connected to a GIC400 are working.

The work and testing were done on a custom SoC so the PR does not include the SoC code since it won't be very useful to anyone.

Closes #6545
Closes #5540

Signed-off-by: Bradley Bolen [email protected]

codecov-io · 2018-08-06T21:28:55Z

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ulfalizer

Just some Kconfig nits.

arch/arm/core/Kconfig

arch/arm/core/cortex_r/Kconfig

arch/arm/core/Kconfig

ulfalizer · 2018-08-06T21:30:51Z

arch/arm/core/cortex_r/Kconfig

+config ISA_THUMB2
+	bool
+	# Omit prompt to signify "hidden" option
+	default n


Redundant default n.

arch/arm/core/cortex_r/Kconfig

galak · 2018-08-06T22:17:24Z

@bbolen have you tried to see if you can port qemu and the xlnx-zynqmp platform?

bbolen · 2018-08-07T13:36:54Z

@ulfalizer Thanks for the comments. Those should all be fixed now.

bbolen · 2018-08-07T13:45:13Z

@galak I saw that yesterday trying to find a way for others to replicate my work. I will keep looking at it, but I can't guarantee when I may have something useful with respect to qemu.

ulfalizer

Kconfig parts look good to me.

pizi-nordic · 2018-08-07T13:56:33Z

drivers/interrupt_controller/gic.c

+#define	GIC_INT_WD				30
+#define	GIC_INT_IRQ				31
+
+#define IRQ_TYPE_NONE			0x00000000


I think that IRQ type should be set by DTS. This means that:

IRQ type definitions have to be exposed as DTS bindings.

YAML files should be updated accordingly.

Driver should set GICD_ICFGn basing on the flags specified in interrupt property.

pizi-nordic · 2018-08-07T14:04:21Z

drivers/interrupt_controller/gic.c

+#define	NO_GIC_INT_PENDING	1023
+
+/* CPU Interrupt numbers */
+#define GIC_INT_GTMR			27


Could we use here names which will be self-descriptive or easy to find in docs? (like GIC_INT_LEGACY_FIQ)

According to the CoreLink™ GIC-400 Generic Interrupt Controller Technical Reference Manual there is no watchdog interrupt at ID 30 (GIC_INT_WD suggests watchdog). Is watchdog on this line specific to your SoC?

IMHO these defines should be exposed to the DTS or some platform code which will use it (like timer driver).

pizi-nordic · 2018-08-07T14:49:51Z

drivers/interrupt_controller/gic.c

+	 * Set priority on PPI and SGI interrupts
+	 */
+	for (i = 0; i < 32; i += 4)
+		sys_write32(0xa0a0a0a0, GICD_IPRIORITYRn + i);


IMHO priority should be taken from DTS.

I see two possible paths to get the flags and priority from gic.c. 1) add an intr_set_priority() callback to the irq_next_level_api struct and call it from arch/arm/core/irq_manage.c:_irq_priority_set() OR 2) redefine _ARCH_IRQ_CONNECT for Cortex-R to pass flags_p instead of 0 to _ISR_DECLARE and get to the flags through the isr_sw_table.

Do you have a preference between these two, or another option?

pizi-nordic · 2018-08-07T14:57:34Z

arch/Kconfig

@@ -19,7 +19,6 @@ config ARC

 config ARM


IMHO subject of the commit does not reflect actual change.
What about "arch: arm: Move thread_abort.c to cortex_m specific directory"?

pizi-nordic · 2018-08-08T09:53:03Z

arch/arm/core/CMakeLists.txt

@@ -4,7 +4,6 @@ zephyr_library_sources(
  exc_exit.S
  swap.c
  swap_helper.S
-  fault.c


Here also you are moving file specific to cortex-m, but subject of the commit suggests cortex-r.

pizi-nordic · 2018-08-08T11:52:45Z

arch/arm/core/isr_wrapper.S

+	 * Cortex-R only has one IRQ line so the main handler will be at
+	 * offset 0 of the table.
+	 */
+	mov r0, #0


Are you going to dispatch FIQ and IRQ using the same IRQ table?

pizi-nordic · 2018-08-08T12:29:45Z

arch/arm/core/swap_helper.S

@@ -140,7 +151,11 @@ SECTION_FUNC(TEXT, __pendsv)
    str r3, [r4]
 #else
    ldr r0, [r2, #_thread_offset_to_basepri]
+#ifdef CONFIG_CPU_CORTEX_M
    movs.n r3, #0


IMHO we just could use "movs r3, #0" on both Cortex-M and Cortex-R

pizi-nordic · 2018-08-08T12:42:00Z

arch/arm/core/swap_helper.S

+    mov r4, lr
+
+    cps #MODE_SYS
+    stmdb sp!, {r0-r4}


What about R12?

arch/arm/core/swap_helper.S

pizi-nordic · 2018-08-08T13:31:19Z

include/arch/arm/cortex_r/asm_inline_gcc.h

@@ -0,0 +1,158 @@
+/* ARM Cortex-M GCC specific public inline assembler functions and macros */


IMHO with some modifications in _arch_irq_lock()/_arch_irq_unlock() this file could be common for Cortex-M and R.

ioannisg

Went through most of the /arch code; added a few comments about re-using code and about Kconfig options.

ioannisg · 2018-08-09T07:38:53Z

arch/arm/core/cortex_r/Kconfig

+config CPU_CORTEX_R4
+	bool
+	select CPU_CORTEX_R
+	select ARMV7_R_ARMV8_R_MAINLINE


Is this the right thing to do?
I mean: for Cortex-M, ARMv8-M_Mainline is a "super-set" of and backwards-compatible with ARMv7-M.
Is this true for ARMv7-R? Do ARMv7-R, ARMv8-R have the Baseline, Mainline versions?

If not, I would say, it is better to name the architecture as ARMV7_R

ioannisg · 2018-08-09T08:20:50Z

arch/arm/core/cortex_r/Kconfig

+
+if CPU_CORTEX_R
+
+config ISA_THUMB2


I agree. There are several options that might be not-specific to ARM-R (instead, shared with ARM-M).
Could we move those options to arm/core/Kconfig, instead?

ioannisg · 2018-08-09T08:30:11Z

arch/arm/core/cortex_r/Kconfig

+	select ATOMIC_OPERATIONS_BUILTIN
+	select ISA_ARM
+	help
+	  This option signifies the use of an ARMv7-R processor


Coming back to this one: is this accurate for ARMv8-R? Are there Baseline and Mainline variations?

ioannisg · 2018-08-09T08:33:01Z

arch/arm/core/cortex_r/exc_manage.c

@@ -0,0 +1,37 @@
+/*


Is this file just copy-pasted from the cortex-m version of it?

arch/arm/core/cortex_r/fault.c

ioannisg · 2018-08-09T08:59:02Z

arch/arm/core/cortex_r/prep_c.c

@@ -0,0 +1,71 @@
+/*


I had a quick look, and it seems to me that the only difference from Cortex-M is that we do not have the code block for the case of CONFIG_CPU_CORTEX_M_HAS_VTOR=y.

ioannisg · 2018-08-09T09:11:11Z

arch/arm/core/cortex_r/reset.S

+SYS_Stack:
+	.skip 1024 * 4
+
+#define STACK_MARGIN		4


...And use them, directly in the linker script, perhaps, @pizi-nordic ?

ioannisg · 2018-08-09T09:15:24Z

arch/arm/core/cortex_r/scb.c

+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+


Could we re-use the Cortex-M scb.c file, instead?
And add this dummy implementation, if ARMv7_R is defined (instead of ARMv-M). Note, that this would move the scb.c one level up.

ioannisg · 2018-08-09T11:20:57Z

arch/arm/core/irq_manage.c

 #include <arch/arm/cortex_m/cmsis.h>
+#else


Perhaps, it is better to have CONFIG_CPU_CORTEX_3 explicitly given, here.

Same applies to more cases, below.

I'm sorry, I think I'm missing something here. I was assuming that this code applied to all Cortex-M's. Are you saying that it should only apply to the M3?

ioannisg · 2018-08-09T11:22:04Z

arch/arm/core/swap.c

 	/* set pending bit to make sure we will take a PendSV exception */
 	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
+#endif

 	/* clear mask or enable all irqs to take a pendsv */
 	irq_unlock(0);


Is this needed for Cortex-R?

bbolen · 2018-08-14T18:14:09Z

@pizi-nordic @ioannisg I've updated this PR with changes to address your comments.

ioannisg

Some more suggestions and issues/questions.

One general thing: Please, use #if defined (), instead of #ifdef in the arm/core and include/ sub-trees

ioannisg · 2018-08-17T12:01:10Z

arch/arm/core/cortex_r/Kconfig

+	help
+	  This option signifies the use of an ARMv7-R processor
+	  implementation, or the use of an ARMv8-R processor
+	  implementation supporting the Main Extension.


Please, clarify: does the -R- architecture have Base and Mainline versions for v8? If not, the help text needs update

Btw, I searched a bit and I didn't see clear indication of Baseline, Mainline terminology outside the -M- architecture...

ioannisg · 2018-08-17T12:02:42Z

arch/arm/core/cortex_r/Kconfig

+	  referred to as a Mainline Implementation.
+	  - ARMv7-R compatibility requires the Main Extension.
+
+	  From https://developer.arm.com/products/architecture/m-profile:


Link points to -M- documentation

ioannisg · 2018-08-17T12:06:48Z

arch/arm/core/cortex_r/Kconfig

+	depends on ARMV7_R
+	help
+	  This option signifies the use of an ARMv7-R processor
+	  implementation, or the use of an ARMv8-R processor


ARMv8 is not reflected in the symbol name.

ioannisg · 2018-08-17T12:07:42Z

arch/arm/core/cortex_r/Kconfig

+	bool
+	select CPU_CORTEX_R
+	select ARMV7_R
+	select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU


ARMV7_M_ARMV8_M_FP is for Cortex-M CPUs

I'm sorry. Most of this is just copy-paste crud that I'll get rid of.

ioannisg · 2018-08-17T12:16:04Z

arch/arm/core/cpu_idle.S

@@ -120,7 +124,8 @@ SECTION_FUNC(TEXT, k_cpu_idle)
 	mov lr, r0
 #endif

-#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \


This, here (and right below on line 180/185) look a bit weird; ARMV7_R is "grouped" together with ARMV6_M, instead of ARMV7_M.

If this is indeed correct, and needs to be as is, it will confuse the reader.
Any suggestion how to address this, @galak ?

ioannisg · 2018-08-17T12:30:06Z

arch/arm/core/exc_exit.S


 #ifdef CONFIG_PREEMPT_ENABLED
    ldr r0, =_kernel

    ldr r1, [r0, #_kernel_offset_to_current]

-    ldr r0, [r0, _kernel_offset_to_ready_q_cache]
+    ldr r0, [r0, #_kernel_offset_to_ready_q_cache]


What was the reason for this?

Using the zephyr-sdk, I get a compile error
src/zephyr/arch/arm/core/exc_exit.S: Assembler messages:
src/zephyr/arch/arm/core/exc_exit.S:82: Error: immediate expression requires a # prefix -- `ldr r0,[r0,(0x1c+0x0)]' since _kernel_offset_to_ready_q_cache is an immediate value. I can't really say why the M boards do not see this.

arch/arm/core/swap_helper.S

ioannisg · 2018-08-17T12:38:38Z

arch/arm/core/swap_helper.S

@@ -140,7 +151,7 @@ SECTION_FUNC(TEXT, __pendsv)
    str r3, [r4]
 #else
    ldr r0, [r2, #_thread_offset_to_basepri]
-    movs.n r3, #0
+    movs r3, #0


what is the reason for this change?

Again, compile error when using the SDK for Cortex-R
src/zephyr/arch/arm/core/swap_helper.S: Assembler messages:
src/zephyr/arch/arm/core/swap_helper.S:158: Error: unexpected character n' in type specifier src/zephyr/arch/arm/core/swap_helper.S:158: Error: bad instruction movs.n r3,#0'

arch/arm/core/isr_wrapper.S

arch/arm/core/prep_c.c

ioannisg · 2019-08-09T08:15:07Z

boards/arm/qemu_cortex_r5/qemu_cortex_r5.yaml

+flash: 256
+testing:
+  default: false
+  ignore_tags:


Not sure why these tags are all ignored

Currently, the cortex R5 on the xlnx-zynmp qemu machine is not hooked up to an interrupt controller, so only the "hello world" test case will run right now.

drivers/serial/Kconfig.xlnx

include/arch/arm/irq.h

ioannisg

Went through the PR, looks OK to me. I still left several comments to address, but, just to try to push this for 2.0, I give a +1

ioannisg · 2019-08-09T08:22:00Z

@bbolen I suppose if you rebase once more you can run CI with the new SDK, Qemu.

ioannisg · 2019-08-09T14:14:25Z

@andrewboie @galak could you have another look?
@bbolen could you rebase to latest master?

Provide a path for irq controller drivers to change properties of an individual irq using priority and flags fields that come from the device tree. Signed-off-by: Bradley Bolen <[email protected]>

The GIC400 is a common interrupt controller that can be used with the Cortex A and R series processors. This patch adds basic interrupt handling for the GIC, but does not handle multiple routing or priorities. Signed-off-by: Bradley Bolen <[email protected]>

This reverts commit e20fd5f. This is needed for Cortex-R support. Signed-off-by: Bradley Bolen <[email protected]>

This adds initial Cortex-R support for interrupts and context switching. Signed-off-by: Bradley Bolen <[email protected]>

Cortex R has a write buffer that can cause reordering problems when accessing memory mapped registers. Use memory barries to make sure that these accesses are performed in the desired order. Signed-off-by: Bradley Bolen <[email protected]>

Pass the correct -march and -mcpu flags to the compiler when building for the Cortex-R4. Signed-off-by: Bradley Bolen <[email protected]>

Pass the correct -mcpu flags to the compiler when building for the Cortex-R5. Signed-off-by: Bradley Bolen <[email protected]>

Add ZynqMP PS uart driver for Xilinx ZynqMP platform Signed-off-by: Wendy Liang <[email protected]>

Add Xilinx PS ttc timer for Xilinx ZynqMP platform. Signed-off-by: Wendy Liang <[email protected]>

This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based platform for Cortex-R based testing. This SoC only supports an interrupt controller and serial port for limited testing. Signed-off-by: Bradley Bolen <[email protected]>

This adds a qemu test board using the Xilinx ZynqMP SoC. Signed-off-by: Bradley Bolen <[email protected]>

The xlnx-zcu102 qemu machine is the only one that supports a Cortex-R processor. However, its main CPUs are Cortex A53s which requires the aarch64 qemu binary to run. Signed-off-by: Bradley Bolen <[email protected]>

bbolen requested review from andrewboie, galak, MaureenHelm, nashif and SebastianBoe as code owners August 6, 2018 20:47

carlescufi requested review from agross-oss and ioannisg August 6, 2018 20:58

carlescufi added DNM This PR should not be merged (Do Not Merge) area: ARM ARM (32-bit) Architecture RFC Request For Comments: want input from the community area: Architectures and removed DNM This PR should not be merged (Do Not Merge) labels Aug 6, 2018

carlescufi requested a review from pizi-nordic August 6, 2018 20:59

ulfalizer suggested changes Aug 6, 2018

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bbolen force-pushed the cortex_r branch from a87639e to 11d1081 Compare August 7, 2018 13:31

ulfalizer approved these changes Aug 7, 2018

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pizi-nordic reviewed Aug 8, 2018

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ioannisg requested changes Aug 9, 2018

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nashif closed this Aug 11, 2018

nashif reopened this Aug 11, 2018

bbolen force-pushed the cortex_r branch 2 times, most recently from a97a908 to 85a8ecf Compare August 14, 2018 18:08

SebastianBoe removed their request for review August 16, 2018 07:39

ioannisg requested changes Aug 17, 2018

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bbolen force-pushed the cortex_r branch from 85a8ecf to f4d02d8 Compare August 21, 2018 12:04

ioannisg reviewed Aug 9, 2019

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arch/arm/core/isr_wrapper.S Show resolved Hide resolved

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ioannisg requested review from galak, wjliang and andrewboie August 9, 2019 08:22

galak mentioned this pull request Aug 9, 2019

2.0 Release Checklist #15494

Closed

48 tasks

Bradley Bolen and others added 12 commits August 9, 2019 10:56

drivers: interrupts: Add a set_priority callback

05433ac

Provide a path for irq controller drivers to change properties of an individual irq using priority and flags fields that come from the device tree. Signed-off-by: Bradley Bolen <[email protected]>

Revert "toolchain: gcc: Remove ref. to undefined sym. CONFIG_ISA_ARM"

1b0cd18

This reverts commit e20fd5f. This is needed for Cortex-R support. Signed-off-by: Bradley Bolen <[email protected]>

arch: arm: Add Cortex-R support

6f81e76

This adds initial Cortex-R support for interrupts and context switching. Signed-off-by: Bradley Bolen <[email protected]>

arch: arm: Add Cortex-R4 support

5f68cd3

Pass the correct -march and -mcpu flags to the compiler when building for the Cortex-R4. Signed-off-by: Bradley Bolen <[email protected]>

arch: arm: Add Cortex-R5 support

8a9048e

Pass the correct -mcpu flags to the compiler when building for the Cortex-R5. Signed-off-by: Bradley Bolen <[email protected]>

serial: Add Xilinx ZynqMP PS uart driver

df84594

Add ZynqMP PS uart driver for Xilinx ZynqMP platform Signed-off-by: Wendy Liang <[email protected]>

timer: Add Xilinx ZynqMP PS ttc timer

00144f4

Add Xilinx PS ttc timer for Xilinx ZynqMP platform. Signed-off-by: Wendy Liang <[email protected]>

soc: arm: xilinx_zynqmp: Add qemu based SoC

7c14465

This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based platform for Cortex-R based testing. This SoC only supports an interrupt controller and serial port for limited testing. Signed-off-by: Bradley Bolen <[email protected]>

boards: qemu_cortex_r5: Add qemu test board for the Cortex-R series

5949236

This adds a qemu test board using the Xilinx ZynqMP SoC. Signed-off-by: Bradley Bolen <[email protected]>

cmake: emu: Allow overriding the qemu binary

8401923

The xlnx-zcu102 qemu machine is the only one that supports a Cortex-R processor. However, its main CPUs are Cortex A53s which requires the aarch64 qemu binary to run. Signed-off-by: Bradley Bolen <[email protected]>

bbolen force-pushed the cortex_r branch from 30670c6 to 8401923 Compare August 9, 2019 15:37

andrewboie approved these changes Aug 9, 2019

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ioannisg merged commit b602e38 into zephyrproject-rtos:master Aug 9, 2019

This was referenced Aug 18, 2019

[Coverity CID :203452]Control flow issues in /drivers/timer/xlnx_psttc_timer.c #18366

Closed

[Coverity CID :203434]Control flow issues in /drivers/timer/xlnx_psttc_timer.c #18365

Closed

bbolen deleted the cortex_r branch February 14, 2022 14:43

		@@ -0,0 +1,158 @@
		/* ARM Cortex-M GCC specific public inline assembler functions and macros */

Initial support for ARM Cortex-R #9316

Initial support for ARM Cortex-R #9316

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ioannisg commented Aug 9, 2019

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