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Overview
Cupertino Miranda edited this page Nov 18, 2020
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| Feature | Observations |
|---|---|
| ISA variations | Only ARCHS, limited ARCEM (see Zero Overhead Loops Instructions). |
| Endianess | Little endian only |
| Register set | Full 32 register set |
| ZOL | Only 32-bit. |
| Atomic operations | In progress. |
| 64-bit load/store | Full support. |
| DIV/REM | Limited support, no DIVZERO exception throw. |
| Swap instructions | Supported. |
| Bitscan instructions | Supported. |
| Code density | No JLI,EI, LDI support. |
| MPY support | Full mpy-option=2 support. |
| Bit shift | Full support. |
| Timer0 | Partial support. See Timers. |
| Timer1 | Partial support. See Timers. |
| RTC | Partial support. See Timers. |
| MMU | Partial support. See MMU. |
| MPU | Partial support. See MPU. |
| Interrupt controller | Partial support. See PIC. |
| Caches | Only dummy AUX registers support. |
Zero Overhead loops are only supported using 32-bit lp_count register configuration. No jump instruction or its delay slot is permitted as the last instruction of the ZOL. This means, not all ARCEM code may run safely on QEMU.
At this moment there is no support or planning to add for DSP, saturated, fast math, and floating point instructions. More about implemented instructions here