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Processor Timers
Yuriy Kolerov edited this page Jul 22, 2023
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2 revisions
The ARC TIMER module supports:
- TIMER0 configuration.
- TIMER1 configuration.
- 64-bit real time counter. However, it doesn't count the CPU cycles, nor can be configured as a Watchdog timer.
All the counters are not counting cycles, but rather the elapsed simulation time related with a heuristic frequency found for ARC CPU frequency. The ARC CPU frequency can be user controlled and changed via QEMU parameter --global cpu.freq_hz=XXXX, where XXXX is the new desired frequency in Hz.
| AUX register | Observations |
|---|---|
| CONTROL0.IE | Fully supported |
| CONTROL0.NH | Not supported |
| CONTROL0.W | Not supported |
| CONTROL0.IP | Fully supported |
| CONTROL0.PD | Not supported |
| COUNT0 | Fully supported |
| LIMIT0 | Fully supported |
| AUX register | Observations |
|---|---|
| CONTROL1.IE | Fully supported |
| CONTROL1.NH | Not supported |
| CONTROL1.W | Not supported |
| CONTROL1.IP | Fully supported |
| CONTROL1.PD | Not supported |
| COUNT1 | Fully supported |
| LIMIT1 | Fully supported |
| AUX register | Observations |
|---|---|
| AUX_RTC_CTRL.E | Fully supported |
| AUX_RTC_CTRL.C | Fully supported |
| AUX_RTC_CTRL.A0 | Always set to 1 |
| AUX_RTC_CTRL.A1 | Always set to 1 |
| AUX_RTC_LOW | Fully supported |
| AUX_RTC_HIGH | Fully supported |
| AUX register | Observations | QEMU properties |
|---|---|---|
| TIMER_BUILD.VERSION | Always set to 4 | |
| TIMER_BUILD.T0 | Fully supported | --global cpu.timer0=true/false |
| TIMER_BUILD.T1 | Fully supported | --global cpu.timer1=true/false |
| TIMER_BUILD.RTC | Fully supported | --global cpu.rtc-opt=true/false |
| TIMER_BUILD.P0 | Not supported | |
| TIMER_BUILD.P1 | Not supported |