stm32: q/o/x-spi bindings generate dtc warnings

[erwango]

Is your enhancement proposal related to a problem? Please describe.
Current STM32 Q/O/X-SPI bindings is not following device tree specification and since #76735 a warning is generated when building platforms enabling Q/O/X-SPI nodes:

CMake Warning at /local/home/frq07517/zephyrproject/zephyr/cmake/modules/dts.cmake:425 (message):
  dtc raised one or more warnings:


  /local/home/frq07517/zephyrproject/zephyr/build/b_u585i_iot02a/zephyr/zephyr.dts:820.26-848.5:
  Warning (spi_bus_bridge): /soc/spi@420d2400: incorrect #size-cells for SPI
  bus

  <stdout>: Warning (spi_bus_reg): Failed prerequisite 'spi_bus_bridge'

This is because we don't respect a device tree (dtc check which is the de facto specification) which states that reg and sizes of SPI devices (nodes sitting on a SPI bus), should be defined as:

      reg = <FOO>;
      size = <BAR>;

ie #size-cells = <0>;

On STM32 SoCs, we're defining them as:

           reg = <FOO BAR>;

ie #size-cells = <1>;. This design was adopted in #68274 which was approved by subsytem maintainer at that time.

Describe the solution you'd like
Review STM32 Q/O/X-SPI devices binding to comply with dts spec and do the same as others socs description vendors, where address is defined in bus node:

           reg = <0x500c8000 0x1000>, <0x90000000 DT_SIZE_M(8)>;

and first two cells are address/size of the controller and last two cells are addressable address/size

[FRASTM]

• qspi bindings
• ospi bindings
• xspi bindings for the stm32 flash and psram xspi drivers : PR stm32 xspi bindings fixes dtc warnings #88646