drivers: eth_esp32: allow selecting ref clk source #65759
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@sylvioalves compliance failure is related to the typo within espressif HAL, how should I fix that? |
mniestroj
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| ref_clk_gpio_output: | ||
| type: int | ||
| enum: | ||
| - 16 | ||
| - 17 | ||
| description: | | ||
| GPIO number to output RMII Clock. |
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How about using standard phandle-array for gpios? e.g. ref-clk-output-gpios = <&gpio0 16 0>;
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I don't see benefits from it since this is not handled by the Zephyr GPIO API but the espressif HAL directly. phandle-array would not be also possible to validate by the YAML parser itself as it is done right now.
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This is about having single way to describe GPIOs in devicetree files, regardless how those are used by driver (and whether Zephyr GPIO API is used or not).
See nordic,nrf-led-matrix.yaml bindings, which uses standard gpios phandles for rows and columns, but internally in the driver just nRF specific representation of GPIOs are used.
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Fair enough, I've changed that into phandle-array with additional build asserts.
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mniestroj
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Bumped hal_espressif to fix the compliance failure. |
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The following west manifest projects have been modified in this Pull Request:
Note: This message is automatically posted and updated by the Manifest GitHub Action. |
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mniestroj
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@bbilas please rebase |
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Done. |
sylvioalves
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@carlescufi It seems that we have not-related compliance failure, see: Error: See https://docs.zephyrproject.org/latest/build/kconfig/tips.html for more details.
Found references to undefined Kconfig symbols. If any of these are false
positives, then add them to UNDEF_KCONFIG_WHITELIST in /home/runner/work/zephyr/zephyr/./scripts/ci/check_compliance.py.
If the reference is for a comment like /* CONFIG_FOO_* */ (or
/* CONFIG_FOO_*_... */), then please use exactly that form (with the '*'). The
CI check knows not to flag it.
More generally, a reference followed by $, @, {, *, or ## will never be
flagged.
CONFIG_ZTEST_NEW_API tests/drivers/console_switching/prj.conf:2
Error: Process completed with exit code 1.
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Rebased with main once again... |
mniestroj
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needs rebase |
It contains a fix for a typo within emac_hal module. Signed-off-by: Bartosz Bilas <[email protected]>
In case of boards where REF_CLK signal is not connected to the GPIO0 by default add the possibility to use the optional GPIO16/GPIO17 as a REF CLK source. Signed-off-by: Bartosz Bilas <[email protected]>
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Done. |
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When GPIO17 or 16 is used as an external REF_CLK signal, the output is enabled in eth_esp32.c This was added in PR number zephyrproject-rtos#65759 and then refined in PR zephyrproject-rtos#74442. However this does not work for PHYs which need the REF_CLK for MDIO communication, such as LAN8720A. In such cases phy_mii driver tries to get the ID of such a PHY before REF_CLK is present. Therefore in this PR I propose to move REF_CLK initialization from eth_esp32.c to mdio_esp32.c which gets initialized before PHY and ETH. Signed-off-by: Łukasz Iwaszkiewicz <[email protected]>
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When GPIO17 or 16 is used as an external REF_CLK signal, the output is enabled in eth_esp32.c This was added in PR number #65759 and then refined in PR #74442. However this does not work for PHYs which need the REF_CLK for MDIO communication, such as LAN8720A. In such cases phy_mii driver tries to get the ID of such a PHY before REF_CLK is present. Therefore in this PR I propose to move REF_CLK initialization from eth_esp32.c to mdio_esp32.c which gets initialized before PHY and ETH. Signed-off-by: Łukasz Iwaszkiewicz <[email protected]>
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When GPIO17 or 16 is used as an external REF_CLK signal, the output is enabled in eth_esp32.c This was added in PR number zephyrproject-rtos#65759 and then refined in PR zephyrproject-rtos#74442. However this does not work for PHYs which need the REF_CLK for MDIO communication, such as LAN8720A. In such cases phy_mii driver tries to get the ID of such a PHY before REF_CLK is present. Therefore in this PR I propose to move REF_CLK initialization from eth_esp32.c to mdio_esp32.c which gets initialized before PHY and ETH. Signed-off-by: Łukasz Iwaszkiewicz <[email protected]>
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In case of boards where REF_CLK signal is not connected to the GPIO0 by default add the possibility to use the optional GPIO16/GPIO17 as a REF CLK source.